1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef FVP_PWRC_H 8*91f16700Schasinglulu #define FVP_PWRC_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu /* FVP Power controller register offset etc */ 11*91f16700Schasinglulu #define PPOFFR_OFF U(0x0) 12*91f16700Schasinglulu #define PPONR_OFF U(0x4) 13*91f16700Schasinglulu #define PCOFFR_OFF U(0x8) 14*91f16700Schasinglulu #define PWKUPR_OFF U(0xc) 15*91f16700Schasinglulu #define PSYSR_OFF U(0x10) 16*91f16700Schasinglulu 17*91f16700Schasinglulu #define PWKUPR_WEN BIT_32(31) 18*91f16700Schasinglulu 19*91f16700Schasinglulu #define PSYSR_AFF_L2 BIT_32(31) 20*91f16700Schasinglulu #define PSYSR_AFF_L1 BIT_32(30) 21*91f16700Schasinglulu #define PSYSR_AFF_L0 BIT_32(29) 22*91f16700Schasinglulu #define PSYSR_WEN BIT_32(28) 23*91f16700Schasinglulu #define PSYSR_PC BIT_32(27) 24*91f16700Schasinglulu #define PSYSR_PP BIT_32(26) 25*91f16700Schasinglulu 26*91f16700Schasinglulu #define PSYSR_WK_SHIFT 24 27*91f16700Schasinglulu #define PSYSR_WK_WIDTH 0x2 28*91f16700Schasinglulu #define PSYSR_WK_MASK ((1U << PSYSR_WK_WIDTH) - 1U) 29*91f16700Schasinglulu #define PSYSR_WK(x) ((x) >> PSYSR_WK_SHIFT) & PSYSR_WK_MASK 30*91f16700Schasinglulu 31*91f16700Schasinglulu #define WKUP_COLD U(0x0) 32*91f16700Schasinglulu #define WKUP_RESET U(0x1) 33*91f16700Schasinglulu #define WKUP_PPONR U(0x2) 34*91f16700Schasinglulu #define WKUP_GICREQ U(0x3) 35*91f16700Schasinglulu 36*91f16700Schasinglulu #define PSYSR_INVALID U(0xffffffff) 37*91f16700Schasinglulu 38*91f16700Schasinglulu #ifndef __ASSEMBLER__ 39*91f16700Schasinglulu 40*91f16700Schasinglulu #include <stdint.h> 41*91f16700Schasinglulu 42*91f16700Schasinglulu /******************************************************************************* 43*91f16700Schasinglulu * Function & variable prototypes 44*91f16700Schasinglulu ******************************************************************************/ 45*91f16700Schasinglulu void fvp_pwrc_write_pcoffr(u_register_t mpidr); 46*91f16700Schasinglulu void fvp_pwrc_write_ppoffr(u_register_t mpidr); 47*91f16700Schasinglulu void fvp_pwrc_write_pponr(u_register_t mpidr); 48*91f16700Schasinglulu void fvp_pwrc_set_wen(u_register_t mpidr); 49*91f16700Schasinglulu void fvp_pwrc_clr_wen(u_register_t mpidr); 50*91f16700Schasinglulu unsigned int fvp_pwrc_read_psysr(u_register_t mpidr); 51*91f16700Schasinglulu unsigned int fvp_pwrc_get_cpu_wkr(u_register_t mpidr); 52*91f16700Schasinglulu 53*91f16700Schasinglulu #endif /*__ASSEMBLER__*/ 54*91f16700Schasinglulu 55*91f16700Schasinglulu #endif /* FVP_PWRC_H */ 56