xref: /arm-trusted-firmware/include/common/bl_common.ld.h (revision 91f16700b400a8c0651d24a598fc48ee2997a0d7)
1*91f16700Schasinglulu /*
2*91f16700Schasinglulu  * Copyright (c) 2020-2022, ARM Limited and Contributors. All rights reserved.
3*91f16700Schasinglulu  *
4*91f16700Schasinglulu  * SPDX-License-Identifier: BSD-3-Clause
5*91f16700Schasinglulu  */
6*91f16700Schasinglulu 
7*91f16700Schasinglulu #ifndef BL_COMMON_LD_H
8*91f16700Schasinglulu #define BL_COMMON_LD_H
9*91f16700Schasinglulu 
10*91f16700Schasinglulu #include <platform_def.h>
11*91f16700Schasinglulu 
12*91f16700Schasinglulu #ifdef __aarch64__
13*91f16700Schasinglulu #define STRUCT_ALIGN	8
14*91f16700Schasinglulu #define BSS_ALIGN	16
15*91f16700Schasinglulu #else
16*91f16700Schasinglulu #define STRUCT_ALIGN	4
17*91f16700Schasinglulu #define BSS_ALIGN	8
18*91f16700Schasinglulu #endif
19*91f16700Schasinglulu 
20*91f16700Schasinglulu #ifndef DATA_ALIGN
21*91f16700Schasinglulu #define DATA_ALIGN	1
22*91f16700Schasinglulu #endif
23*91f16700Schasinglulu 
24*91f16700Schasinglulu #define CPU_OPS						\
25*91f16700Schasinglulu 	. = ALIGN(STRUCT_ALIGN);			\
26*91f16700Schasinglulu 	__CPU_OPS_START__ = .;				\
27*91f16700Schasinglulu 	KEEP(*(.cpu_ops))				\
28*91f16700Schasinglulu 	__CPU_OPS_END__ = .;
29*91f16700Schasinglulu 
30*91f16700Schasinglulu #define PARSER_LIB_DESCS				\
31*91f16700Schasinglulu 	. = ALIGN(STRUCT_ALIGN);			\
32*91f16700Schasinglulu 	__PARSER_LIB_DESCS_START__ = .;			\
33*91f16700Schasinglulu 	KEEP(*(.img_parser_lib_descs))			\
34*91f16700Schasinglulu 	__PARSER_LIB_DESCS_END__ = .;
35*91f16700Schasinglulu 
36*91f16700Schasinglulu #define RT_SVC_DESCS					\
37*91f16700Schasinglulu 	. = ALIGN(STRUCT_ALIGN);			\
38*91f16700Schasinglulu 	__RT_SVC_DESCS_START__ = .;			\
39*91f16700Schasinglulu 	KEEP(*(.rt_svc_descs))				\
40*91f16700Schasinglulu 	__RT_SVC_DESCS_END__ = .;
41*91f16700Schasinglulu 
42*91f16700Schasinglulu #if SPMC_AT_EL3
43*91f16700Schasinglulu #define EL3_LP_DESCS					\
44*91f16700Schasinglulu 	. = ALIGN(STRUCT_ALIGN);			\
45*91f16700Schasinglulu 	__EL3_LP_DESCS_START__ = .;			\
46*91f16700Schasinglulu 	KEEP(*(.el3_lp_descs))				\
47*91f16700Schasinglulu 	__EL3_LP_DESCS_END__ = .;
48*91f16700Schasinglulu #else
49*91f16700Schasinglulu #define EL3_LP_DESCS
50*91f16700Schasinglulu #endif
51*91f16700Schasinglulu 
52*91f16700Schasinglulu #if ENABLE_SPMD_LP
53*91f16700Schasinglulu #define SPMD_LP_DESCS					\
54*91f16700Schasinglulu 	. = ALIGN(STRUCT_ALIGN);			\
55*91f16700Schasinglulu 	__SPMD_LP_DESCS_START__ = .;			\
56*91f16700Schasinglulu 	KEEP(*(.spmd_lp_descs))			\
57*91f16700Schasinglulu 	__SPMD_LP_DESCS_END__ = .;
58*91f16700Schasinglulu #else
59*91f16700Schasinglulu #define SPMD_LP_DESCS
60*91f16700Schasinglulu #endif
61*91f16700Schasinglulu #define PMF_SVC_DESCS					\
62*91f16700Schasinglulu 	. = ALIGN(STRUCT_ALIGN);			\
63*91f16700Schasinglulu 	__PMF_SVC_DESCS_START__ = .;			\
64*91f16700Schasinglulu 	KEEP(*(.pmf_svc_descs))				\
65*91f16700Schasinglulu 	__PMF_SVC_DESCS_END__ = .;
66*91f16700Schasinglulu 
67*91f16700Schasinglulu #define FCONF_POPULATOR					\
68*91f16700Schasinglulu 	. = ALIGN(STRUCT_ALIGN);			\
69*91f16700Schasinglulu 	__FCONF_POPULATOR_START__ = .;			\
70*91f16700Schasinglulu 	KEEP(*(.fconf_populator))			\
71*91f16700Schasinglulu 	__FCONF_POPULATOR_END__ = .;
72*91f16700Schasinglulu 
73*91f16700Schasinglulu /*
74*91f16700Schasinglulu  * Keep the .got section in the RO section as it is patched prior to enabling
75*91f16700Schasinglulu  * the MMU and having the .got in RO is better for security. GOT is a table of
76*91f16700Schasinglulu  * addresses so ensure pointer size alignment.
77*91f16700Schasinglulu  */
78*91f16700Schasinglulu #define GOT						\
79*91f16700Schasinglulu 	. = ALIGN(STRUCT_ALIGN);			\
80*91f16700Schasinglulu 	__GOT_START__ = .;				\
81*91f16700Schasinglulu 	*(.got)						\
82*91f16700Schasinglulu 	__GOT_END__ = .;
83*91f16700Schasinglulu 
84*91f16700Schasinglulu /*
85*91f16700Schasinglulu  * The base xlat table
86*91f16700Schasinglulu  *
87*91f16700Schasinglulu  * It is put into the rodata section if PLAT_RO_XLAT_TABLES=1,
88*91f16700Schasinglulu  * or into the bss section otherwise.
89*91f16700Schasinglulu  */
90*91f16700Schasinglulu #define BASE_XLAT_TABLE					\
91*91f16700Schasinglulu 	. = ALIGN(16);					\
92*91f16700Schasinglulu 	__BASE_XLAT_TABLE_START__ = .;			\
93*91f16700Schasinglulu 	*(.base_xlat_table)				\
94*91f16700Schasinglulu 	__BASE_XLAT_TABLE_END__ = .;
95*91f16700Schasinglulu 
96*91f16700Schasinglulu #if PLAT_RO_XLAT_TABLES
97*91f16700Schasinglulu #define BASE_XLAT_TABLE_RO		BASE_XLAT_TABLE
98*91f16700Schasinglulu #define BASE_XLAT_TABLE_BSS
99*91f16700Schasinglulu #else
100*91f16700Schasinglulu #define BASE_XLAT_TABLE_RO
101*91f16700Schasinglulu #define BASE_XLAT_TABLE_BSS		BASE_XLAT_TABLE
102*91f16700Schasinglulu #endif
103*91f16700Schasinglulu 
104*91f16700Schasinglulu #define RODATA_COMMON					\
105*91f16700Schasinglulu 	RT_SVC_DESCS					\
106*91f16700Schasinglulu 	FCONF_POPULATOR					\
107*91f16700Schasinglulu 	PMF_SVC_DESCS					\
108*91f16700Schasinglulu 	PARSER_LIB_DESCS				\
109*91f16700Schasinglulu 	CPU_OPS						\
110*91f16700Schasinglulu 	GOT						\
111*91f16700Schasinglulu 	BASE_XLAT_TABLE_RO				\
112*91f16700Schasinglulu 	EL3_LP_DESCS					\
113*91f16700Schasinglulu 	SPMD_LP_DESCS
114*91f16700Schasinglulu 
115*91f16700Schasinglulu /*
116*91f16700Schasinglulu  * .data must be placed at a lower address than the stacks if the stack
117*91f16700Schasinglulu  * protector is enabled. Alternatively, the .data.stack_protector_canary
118*91f16700Schasinglulu  * section can be placed independently of the main .data section.
119*91f16700Schasinglulu  */
120*91f16700Schasinglulu #define DATA_SECTION					\
121*91f16700Schasinglulu 	.data . : ALIGN(DATA_ALIGN) {			\
122*91f16700Schasinglulu 		__DATA_START__ = .;			\
123*91f16700Schasinglulu 		*(SORT_BY_ALIGNMENT(.data*))		\
124*91f16700Schasinglulu 		__DATA_END__ = .;			\
125*91f16700Schasinglulu 	}
126*91f16700Schasinglulu 
127*91f16700Schasinglulu /*
128*91f16700Schasinglulu  * .rela.dyn needs to come after .data for the read-elf utility to parse
129*91f16700Schasinglulu  * this section correctly.
130*91f16700Schasinglulu  */
131*91f16700Schasinglulu #if __aarch64__
132*91f16700Schasinglulu #define RELA_DYN_NAME		.rela.dyn
133*91f16700Schasinglulu #define RELOC_SECTIONS_PATTERN	*(.rela*)
134*91f16700Schasinglulu #else
135*91f16700Schasinglulu #define RELA_DYN_NAME		.rel.dyn
136*91f16700Schasinglulu #define RELOC_SECTIONS_PATTERN	*(.rel*)
137*91f16700Schasinglulu #endif
138*91f16700Schasinglulu 
139*91f16700Schasinglulu #define RELA_SECTION					\
140*91f16700Schasinglulu 	RELA_DYN_NAME : ALIGN(STRUCT_ALIGN) {		\
141*91f16700Schasinglulu 		__RELA_START__ = .;			\
142*91f16700Schasinglulu 		RELOC_SECTIONS_PATTERN			\
143*91f16700Schasinglulu 		__RELA_END__ = .;			\
144*91f16700Schasinglulu 	}
145*91f16700Schasinglulu 
146*91f16700Schasinglulu #if !(defined(IMAGE_BL31) && RECLAIM_INIT_CODE)
147*91f16700Schasinglulu #define STACK_SECTION					\
148*91f16700Schasinglulu 	.stacks (NOLOAD) : {				\
149*91f16700Schasinglulu 		__STACKS_START__ = .;			\
150*91f16700Schasinglulu 		*(.tzfw_normal_stacks)			\
151*91f16700Schasinglulu 		__STACKS_END__ = .;			\
152*91f16700Schasinglulu 	}
153*91f16700Schasinglulu #endif
154*91f16700Schasinglulu 
155*91f16700Schasinglulu /*
156*91f16700Schasinglulu  * If BL doesn't use any bakery lock then __PERCPU_BAKERY_LOCK_SIZE__
157*91f16700Schasinglulu  * will be zero. For this reason, the only two valid values for
158*91f16700Schasinglulu  * __PERCPU_BAKERY_LOCK_SIZE__ are 0 or the platform defined value
159*91f16700Schasinglulu  * PLAT_PERCPU_BAKERY_LOCK_SIZE.
160*91f16700Schasinglulu  */
161*91f16700Schasinglulu #ifdef PLAT_PERCPU_BAKERY_LOCK_SIZE
162*91f16700Schasinglulu #define BAKERY_LOCK_SIZE_CHECK				\
163*91f16700Schasinglulu 	ASSERT((__PERCPU_BAKERY_LOCK_SIZE__ == 0) ||	\
164*91f16700Schasinglulu 	       (__PERCPU_BAKERY_LOCK_SIZE__ == PLAT_PERCPU_BAKERY_LOCK_SIZE), \
165*91f16700Schasinglulu 	       "PLAT_PERCPU_BAKERY_LOCK_SIZE does not match bakery lock requirements");
166*91f16700Schasinglulu #else
167*91f16700Schasinglulu #define BAKERY_LOCK_SIZE_CHECK
168*91f16700Schasinglulu #endif
169*91f16700Schasinglulu 
170*91f16700Schasinglulu /*
171*91f16700Schasinglulu  * Bakery locks are stored in normal .bss memory
172*91f16700Schasinglulu  *
173*91f16700Schasinglulu  * Each lock's data is spread across multiple cache lines, one per CPU,
174*91f16700Schasinglulu  * but multiple locks can share the same cache line.
175*91f16700Schasinglulu  * The compiler will allocate enough memory for one CPU's bakery locks,
176*91f16700Schasinglulu  * the remaining cache lines are allocated by the linker script
177*91f16700Schasinglulu  */
178*91f16700Schasinglulu #if !USE_COHERENT_MEM
179*91f16700Schasinglulu #define BAKERY_LOCK_NORMAL				\
180*91f16700Schasinglulu 	. = ALIGN(CACHE_WRITEBACK_GRANULE);		\
181*91f16700Schasinglulu 	__BAKERY_LOCK_START__ = .;			\
182*91f16700Schasinglulu 	__PERCPU_BAKERY_LOCK_START__ = .;		\
183*91f16700Schasinglulu 	*(.bakery_lock)					\
184*91f16700Schasinglulu 	. = ALIGN(CACHE_WRITEBACK_GRANULE);		\
185*91f16700Schasinglulu 	__PERCPU_BAKERY_LOCK_END__ = .;			\
186*91f16700Schasinglulu 	__PERCPU_BAKERY_LOCK_SIZE__ = ABSOLUTE(__PERCPU_BAKERY_LOCK_END__ - __PERCPU_BAKERY_LOCK_START__); \
187*91f16700Schasinglulu 	. = . + (__PERCPU_BAKERY_LOCK_SIZE__ * (PLATFORM_CORE_COUNT - 1)); \
188*91f16700Schasinglulu 	__BAKERY_LOCK_END__ = .;			\
189*91f16700Schasinglulu 	BAKERY_LOCK_SIZE_CHECK
190*91f16700Schasinglulu #else
191*91f16700Schasinglulu #define BAKERY_LOCK_NORMAL
192*91f16700Schasinglulu #endif
193*91f16700Schasinglulu 
194*91f16700Schasinglulu /*
195*91f16700Schasinglulu  * Time-stamps are stored in normal .bss memory
196*91f16700Schasinglulu  *
197*91f16700Schasinglulu  * The compiler will allocate enough memory for one CPU's time-stamps,
198*91f16700Schasinglulu  * the remaining memory for other CPUs is allocated by the
199*91f16700Schasinglulu  * linker script
200*91f16700Schasinglulu  */
201*91f16700Schasinglulu #define PMF_TIMESTAMP					\
202*91f16700Schasinglulu 	. = ALIGN(CACHE_WRITEBACK_GRANULE);		\
203*91f16700Schasinglulu 	__PMF_TIMESTAMP_START__ = .;			\
204*91f16700Schasinglulu 	KEEP(*(.pmf_timestamp_array))			\
205*91f16700Schasinglulu 	. = ALIGN(CACHE_WRITEBACK_GRANULE);		\
206*91f16700Schasinglulu 	__PMF_PERCPU_TIMESTAMP_END__ = .;		\
207*91f16700Schasinglulu 	__PERCPU_TIMESTAMP_SIZE__ = ABSOLUTE(. - __PMF_TIMESTAMP_START__); \
208*91f16700Schasinglulu 	. = . + (__PERCPU_TIMESTAMP_SIZE__ * (PLATFORM_CORE_COUNT - 1)); \
209*91f16700Schasinglulu 	__PMF_TIMESTAMP_END__ = .;
210*91f16700Schasinglulu 
211*91f16700Schasinglulu 
212*91f16700Schasinglulu /*
213*91f16700Schasinglulu  * The .bss section gets initialised to 0 at runtime.
214*91f16700Schasinglulu  * Its base address has bigger alignment for better performance of the
215*91f16700Schasinglulu  * zero-initialization code.
216*91f16700Schasinglulu  */
217*91f16700Schasinglulu #define BSS_SECTION					\
218*91f16700Schasinglulu 	.bss (NOLOAD) : ALIGN(BSS_ALIGN) {		\
219*91f16700Schasinglulu 		__BSS_START__ = .;			\
220*91f16700Schasinglulu 		*(SORT_BY_ALIGNMENT(.bss*))		\
221*91f16700Schasinglulu 		*(COMMON)				\
222*91f16700Schasinglulu 		BAKERY_LOCK_NORMAL			\
223*91f16700Schasinglulu 		PMF_TIMESTAMP				\
224*91f16700Schasinglulu 		BASE_XLAT_TABLE_BSS			\
225*91f16700Schasinglulu 		__BSS_END__ = .;			\
226*91f16700Schasinglulu 	}
227*91f16700Schasinglulu 
228*91f16700Schasinglulu /*
229*91f16700Schasinglulu  * The .xlat_table section is for full, aligned page tables (4K).
230*91f16700Schasinglulu  * Removing them from .bss avoids forcing 4K alignment on
231*91f16700Schasinglulu  * the .bss section. The tables are initialized to zero by the translation
232*91f16700Schasinglulu  * tables library.
233*91f16700Schasinglulu  */
234*91f16700Schasinglulu #define XLAT_TABLE_SECTION				\
235*91f16700Schasinglulu 	.xlat_table (NOLOAD) : {				\
236*91f16700Schasinglulu 		__XLAT_TABLE_START__ = .;		\
237*91f16700Schasinglulu 		*(.xlat_table)				\
238*91f16700Schasinglulu 		__XLAT_TABLE_END__ = .;			\
239*91f16700Schasinglulu 	}
240*91f16700Schasinglulu 
241*91f16700Schasinglulu #endif /* BL_COMMON_LD_H */
242