1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2022, ARM Limited. All rights reserved. 3*91f16700Schasinglulu * Copyright (c) 2023, NVIDIA Corporation. All rights reserved. 4*91f16700Schasinglulu * 5*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 6*91f16700Schasinglulu */ 7*91f16700Schasinglulu 8*91f16700Schasinglulu #ifndef TRAP_HANDLE_H 9*91f16700Schasinglulu #define TRAP_HANDLE_H 10*91f16700Schasinglulu 11*91f16700Schasinglulu #include <stdbool.h> 12*91f16700Schasinglulu #include <context.h> 13*91f16700Schasinglulu 14*91f16700Schasinglulu #define ISS_SYSREG_OPCODE_MASK 0x3ffc1eUL 15*91f16700Schasinglulu #define ISS_SYSREG_REG_MASK 0x0003e0UL 16*91f16700Schasinglulu #define ISS_SYSREG_REG_SHIFT 5U 17*91f16700Schasinglulu #define ISS_SYSREG_DIRECTION_MASK 0x000001UL 18*91f16700Schasinglulu 19*91f16700Schasinglulu #define ISS_SYSREG_OPCODE_RNDR 0x30c808U 20*91f16700Schasinglulu #define ISS_SYSREG_OPCODE_IMPDEF 0x303c00U 21*91f16700Schasinglulu #define ISS_SYSREG_OPCODE_RNDRRS 0x32c808U 22*91f16700Schasinglulu 23*91f16700Schasinglulu #define TRAP_RET_UNHANDLED -1 24*91f16700Schasinglulu #define TRAP_RET_REPEAT 0 25*91f16700Schasinglulu #define TRAP_RET_CONTINUE 1 26*91f16700Schasinglulu 27*91f16700Schasinglulu #ifndef __ASSEMBLER__ 28*91f16700Schasinglulu static inline unsigned int get_sysreg_iss_rt(uint64_t esr) 29*91f16700Schasinglulu { 30*91f16700Schasinglulu return (esr & ISS_SYSREG_REG_MASK) >> ISS_SYSREG_REG_SHIFT; 31*91f16700Schasinglulu } 32*91f16700Schasinglulu 33*91f16700Schasinglulu static inline bool is_sysreg_iss_write(uint64_t esr) 34*91f16700Schasinglulu { 35*91f16700Schasinglulu return !(esr & ISS_SYSREG_DIRECTION_MASK); 36*91f16700Schasinglulu } 37*91f16700Schasinglulu 38*91f16700Schasinglulu /** 39*91f16700Schasinglulu * handle_sysreg_trap() - Handle AArch64 system register traps from lower ELs 40*91f16700Schasinglulu * @esr_el3: The content of ESR_EL3, containing the trap syndrome information 41*91f16700Schasinglulu * @ctx: Pointer to the lower EL context, containing saved registers 42*91f16700Schasinglulu * 43*91f16700Schasinglulu * Called by the exception handler when a synchronous trap identifies as a 44*91f16700Schasinglulu * system register trap (EC=0x18). ESR contains the encoding of the op[x] and 45*91f16700Schasinglulu * CRm/CRn fields, to identify the system register, and the target/source 46*91f16700Schasinglulu * GPR plus the direction (MRS/MSR). The lower EL's context can be altered 47*91f16700Schasinglulu * by the function, to inject back the result of the emulation. 48*91f16700Schasinglulu * 49*91f16700Schasinglulu * Return: indication how to proceed with the trap: 50*91f16700Schasinglulu * TRAP_RET_UNHANDLED(-1): trap is unhandled, trigger panic 51*91f16700Schasinglulu * TRAP_RET_REPEAT(0): trap was handled, return to the trapping instruction 52*91f16700Schasinglulu * (repeating it) 53*91f16700Schasinglulu * TRAP_RET_CONTINUE(1): trap was handled, return to the next instruction 54*91f16700Schasinglulu * (continuing after it) 55*91f16700Schasinglulu */ 56*91f16700Schasinglulu int handle_sysreg_trap(uint64_t esr_el3, cpu_context_t *ctx); 57*91f16700Schasinglulu 58*91f16700Schasinglulu /* Prototypes for system register emulation handlers provided by platforms. */ 59*91f16700Schasinglulu int plat_handle_impdef_trap(uint64_t esr_el3, cpu_context_t *ctx); 60*91f16700Schasinglulu int plat_handle_rng_trap(uint64_t esr_el3, cpu_context_t *ctx); 61*91f16700Schasinglulu 62*91f16700Schasinglulu #endif /* __ASSEMBLER__ */ 63*91f16700Schasinglulu 64*91f16700Schasinglulu #endif 65