xref: /arm-trusted-firmware/fdts/stm32mp157c-ed1.dts (revision 91f16700b400a8c0651d24a598fc48ee2997a0d7)
1*91f16700Schasinglulu// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2*91f16700Schasinglulu/*
3*91f16700Schasinglulu * Copyright (c) 2017-2023, STMicroelectronics - All Rights Reserved
4*91f16700Schasinglulu * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
5*91f16700Schasinglulu */
6*91f16700Schasinglulu/dts-v1/;
7*91f16700Schasinglulu
8*91f16700Schasinglulu#include "stm32mp157.dtsi"
9*91f16700Schasinglulu#include "stm32mp15xc.dtsi"
10*91f16700Schasinglulu#include "stm32mp15-pinctrl.dtsi"
11*91f16700Schasinglulu#include "stm32mp15xxaa-pinctrl.dtsi"
12*91f16700Schasinglulu#include <dt-bindings/clock/stm32mp1-clksrc.h>
13*91f16700Schasinglulu#include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi"
14*91f16700Schasinglulu
15*91f16700Schasinglulu/ {
16*91f16700Schasinglulu	model = "STMicroelectronics STM32MP157C eval daughter";
17*91f16700Schasinglulu	compatible = "st,stm32mp157c-ed1", "st,stm32mp157";
18*91f16700Schasinglulu
19*91f16700Schasinglulu	aliases {
20*91f16700Schasinglulu		serial0 = &uart4;
21*91f16700Schasinglulu	};
22*91f16700Schasinglulu
23*91f16700Schasinglulu	chosen {
24*91f16700Schasinglulu		stdout-path = "serial0:115200n8";
25*91f16700Schasinglulu	};
26*91f16700Schasinglulu
27*91f16700Schasinglulu	memory@c0000000 {
28*91f16700Schasinglulu		device_type = "memory";
29*91f16700Schasinglulu		reg = <0xC0000000 0x40000000>;
30*91f16700Schasinglulu	};
31*91f16700Schasinglulu};
32*91f16700Schasinglulu
33*91f16700Schasinglulu&bsec {
34*91f16700Schasinglulu	board_id: board_id@ec {
35*91f16700Schasinglulu		reg = <0xec 0x4>;
36*91f16700Schasinglulu		st,non-secure-otp;
37*91f16700Schasinglulu	};
38*91f16700Schasinglulu};
39*91f16700Schasinglulu
40*91f16700Schasinglulu&clk_hse {
41*91f16700Schasinglulu	st,digbypass;
42*91f16700Schasinglulu};
43*91f16700Schasinglulu
44*91f16700Schasinglulu&cpu0 {
45*91f16700Schasinglulu	cpu-supply = <&vddcore>;
46*91f16700Schasinglulu};
47*91f16700Schasinglulu
48*91f16700Schasinglulu&cpu1 {
49*91f16700Schasinglulu	cpu-supply = <&vddcore>;
50*91f16700Schasinglulu};
51*91f16700Schasinglulu
52*91f16700Schasinglulu&cryp1 {
53*91f16700Schasinglulu	status = "okay";
54*91f16700Schasinglulu};
55*91f16700Schasinglulu
56*91f16700Schasinglulu&hash1 {
57*91f16700Schasinglulu	status = "okay";
58*91f16700Schasinglulu};
59*91f16700Schasinglulu
60*91f16700Schasinglulu&i2c4 {
61*91f16700Schasinglulu	pinctrl-names = "default";
62*91f16700Schasinglulu	pinctrl-0 = <&i2c4_pins_a>;
63*91f16700Schasinglulu	i2c-scl-rising-time-ns = <185>;
64*91f16700Schasinglulu	i2c-scl-falling-time-ns = <20>;
65*91f16700Schasinglulu	clock-frequency = <400000>;
66*91f16700Schasinglulu	status = "okay";
67*91f16700Schasinglulu
68*91f16700Schasinglulu	pmic: stpmic@33 {
69*91f16700Schasinglulu		compatible = "st,stpmic1";
70*91f16700Schasinglulu		reg = <0x33>;
71*91f16700Schasinglulu		interrupts-extended = <&exti_pwr 55 IRQ_TYPE_EDGE_FALLING>;
72*91f16700Schasinglulu		interrupt-controller;
73*91f16700Schasinglulu		#interrupt-cells = <2>;
74*91f16700Schasinglulu		status = "okay";
75*91f16700Schasinglulu
76*91f16700Schasinglulu		regulators {
77*91f16700Schasinglulu			compatible = "st,stpmic1-regulators";
78*91f16700Schasinglulu			ldo1-supply = <&v3v3>;
79*91f16700Schasinglulu			ldo2-supply = <&v3v3>;
80*91f16700Schasinglulu			ldo3-supply = <&vdd_ddr>;
81*91f16700Schasinglulu			ldo5-supply = <&v3v3>;
82*91f16700Schasinglulu			ldo6-supply = <&v3v3>;
83*91f16700Schasinglulu			pwr_sw1-supply = <&bst_out>;
84*91f16700Schasinglulu			pwr_sw2-supply = <&bst_out>;
85*91f16700Schasinglulu
86*91f16700Schasinglulu			vddcore: buck1 {
87*91f16700Schasinglulu				regulator-name = "vddcore";
88*91f16700Schasinglulu				regulator-min-microvolt = <1200000>;
89*91f16700Schasinglulu				regulator-max-microvolt = <1350000>;
90*91f16700Schasinglulu				regulator-always-on;
91*91f16700Schasinglulu				regulator-initial-mode = <0>;
92*91f16700Schasinglulu				regulator-over-current-protection;
93*91f16700Schasinglulu			};
94*91f16700Schasinglulu
95*91f16700Schasinglulu			vdd_ddr: buck2 {
96*91f16700Schasinglulu				regulator-name = "vdd_ddr";
97*91f16700Schasinglulu				regulator-min-microvolt = <1350000>;
98*91f16700Schasinglulu				regulator-max-microvolt = <1350000>;
99*91f16700Schasinglulu				regulator-always-on;
100*91f16700Schasinglulu				regulator-initial-mode = <0>;
101*91f16700Schasinglulu				regulator-over-current-protection;
102*91f16700Schasinglulu			};
103*91f16700Schasinglulu
104*91f16700Schasinglulu			vdd: buck3 {
105*91f16700Schasinglulu				regulator-name = "vdd";
106*91f16700Schasinglulu				regulator-min-microvolt = <3300000>;
107*91f16700Schasinglulu				regulator-max-microvolt = <3300000>;
108*91f16700Schasinglulu				regulator-always-on;
109*91f16700Schasinglulu				st,mask-reset;
110*91f16700Schasinglulu				regulator-initial-mode = <0>;
111*91f16700Schasinglulu				regulator-over-current-protection;
112*91f16700Schasinglulu			};
113*91f16700Schasinglulu
114*91f16700Schasinglulu			v3v3: buck4 {
115*91f16700Schasinglulu				regulator-name = "v3v3";
116*91f16700Schasinglulu				regulator-min-microvolt = <3300000>;
117*91f16700Schasinglulu				regulator-max-microvolt = <3300000>;
118*91f16700Schasinglulu				regulator-always-on;
119*91f16700Schasinglulu				regulator-over-current-protection;
120*91f16700Schasinglulu				regulator-initial-mode = <0>;
121*91f16700Schasinglulu			};
122*91f16700Schasinglulu
123*91f16700Schasinglulu			vdda: ldo1 {
124*91f16700Schasinglulu				regulator-name = "vdda";
125*91f16700Schasinglulu				regulator-min-microvolt = <2900000>;
126*91f16700Schasinglulu				regulator-max-microvolt = <2900000>;
127*91f16700Schasinglulu			};
128*91f16700Schasinglulu
129*91f16700Schasinglulu			v2v8: ldo2 {
130*91f16700Schasinglulu				regulator-name = "v2v8";
131*91f16700Schasinglulu				regulator-min-microvolt = <2800000>;
132*91f16700Schasinglulu				regulator-max-microvolt = <2800000>;
133*91f16700Schasinglulu			};
134*91f16700Schasinglulu
135*91f16700Schasinglulu			vtt_ddr: ldo3 {
136*91f16700Schasinglulu				regulator-name = "vtt_ddr";
137*91f16700Schasinglulu				regulator-always-on;
138*91f16700Schasinglulu				regulator-over-current-protection;
139*91f16700Schasinglulu				st,regulator-sink-source;
140*91f16700Schasinglulu			};
141*91f16700Schasinglulu
142*91f16700Schasinglulu			vdd_usb: ldo4 {
143*91f16700Schasinglulu				regulator-name = "vdd_usb";
144*91f16700Schasinglulu				regulator-min-microvolt = <3300000>;
145*91f16700Schasinglulu				regulator-max-microvolt = <3300000>;
146*91f16700Schasinglulu			};
147*91f16700Schasinglulu
148*91f16700Schasinglulu			vdd_sd: ldo5 {
149*91f16700Schasinglulu				regulator-name = "vdd_sd";
150*91f16700Schasinglulu				regulator-min-microvolt = <2900000>;
151*91f16700Schasinglulu				regulator-max-microvolt = <2900000>;
152*91f16700Schasinglulu				regulator-boot-on;
153*91f16700Schasinglulu			};
154*91f16700Schasinglulu
155*91f16700Schasinglulu			v1v8: ldo6 {
156*91f16700Schasinglulu				regulator-name = "v1v8";
157*91f16700Schasinglulu				regulator-min-microvolt = <1800000>;
158*91f16700Schasinglulu				regulator-max-microvolt = <1800000>;
159*91f16700Schasinglulu			};
160*91f16700Schasinglulu
161*91f16700Schasinglulu			vref_ddr: vref_ddr {
162*91f16700Schasinglulu				regulator-name = "vref_ddr";
163*91f16700Schasinglulu				regulator-always-on;
164*91f16700Schasinglulu			};
165*91f16700Schasinglulu
166*91f16700Schasinglulu			bst_out: boost {
167*91f16700Schasinglulu				regulator-name = "bst_out";
168*91f16700Schasinglulu			};
169*91f16700Schasinglulu
170*91f16700Schasinglulu			vbus_otg: pwr_sw1 {
171*91f16700Schasinglulu				regulator-name = "vbus_otg";
172*91f16700Schasinglulu			};
173*91f16700Schasinglulu
174*91f16700Schasinglulu			vbus_sw: pwr_sw2 {
175*91f16700Schasinglulu				regulator-name = "vbus_sw";
176*91f16700Schasinglulu				regulator-active-discharge = <1>;
177*91f16700Schasinglulu			};
178*91f16700Schasinglulu		};
179*91f16700Schasinglulu	};
180*91f16700Schasinglulu};
181*91f16700Schasinglulu
182*91f16700Schasinglulu&iwdg2 {
183*91f16700Schasinglulu	timeout-sec = <32>;
184*91f16700Schasinglulu	status = "okay";
185*91f16700Schasinglulu};
186*91f16700Schasinglulu
187*91f16700Schasinglulu&pwr_regulators {
188*91f16700Schasinglulu	vdd-supply = <&vdd>;
189*91f16700Schasinglulu	vdd_3v3_usbfs-supply = <&vdd_usb>;
190*91f16700Schasinglulu};
191*91f16700Schasinglulu
192*91f16700Schasinglulu&rcc {
193*91f16700Schasinglulu	st,clksrc = <
194*91f16700Schasinglulu		CLK_MPU_PLL1P
195*91f16700Schasinglulu		CLK_AXI_PLL2P
196*91f16700Schasinglulu		CLK_MCU_PLL3P
197*91f16700Schasinglulu		CLK_PLL12_HSE
198*91f16700Schasinglulu		CLK_PLL3_HSE
199*91f16700Schasinglulu		CLK_PLL4_HSE
200*91f16700Schasinglulu		CLK_RTC_LSE
201*91f16700Schasinglulu		CLK_MCO1_DISABLED
202*91f16700Schasinglulu		CLK_MCO2_DISABLED
203*91f16700Schasinglulu	>;
204*91f16700Schasinglulu
205*91f16700Schasinglulu	st,clkdiv = <
206*91f16700Schasinglulu		1 /*MPU*/
207*91f16700Schasinglulu		0 /*AXI*/
208*91f16700Schasinglulu		0 /*MCU*/
209*91f16700Schasinglulu		1 /*APB1*/
210*91f16700Schasinglulu		1 /*APB2*/
211*91f16700Schasinglulu		1 /*APB3*/
212*91f16700Schasinglulu		1 /*APB4*/
213*91f16700Schasinglulu		2 /*APB5*/
214*91f16700Schasinglulu		23 /*RTC*/
215*91f16700Schasinglulu		0 /*MCO1*/
216*91f16700Schasinglulu		0 /*MCO2*/
217*91f16700Schasinglulu	>;
218*91f16700Schasinglulu
219*91f16700Schasinglulu	st,pkcs = <
220*91f16700Schasinglulu		CLK_CKPER_HSE
221*91f16700Schasinglulu		CLK_FMC_ACLK
222*91f16700Schasinglulu		CLK_QSPI_ACLK
223*91f16700Schasinglulu		CLK_ETH_PLL4P
224*91f16700Schasinglulu		CLK_SDMMC12_PLL4P
225*91f16700Schasinglulu		CLK_DSI_DSIPLL
226*91f16700Schasinglulu		CLK_STGEN_HSE
227*91f16700Schasinglulu		CLK_USBPHY_HSE
228*91f16700Schasinglulu		CLK_SPI2S1_PLL3Q
229*91f16700Schasinglulu		CLK_SPI2S23_PLL3Q
230*91f16700Schasinglulu		CLK_SPI45_HSI
231*91f16700Schasinglulu		CLK_SPI6_HSI
232*91f16700Schasinglulu		CLK_I2C46_HSI
233*91f16700Schasinglulu		CLK_SDMMC3_PLL4P
234*91f16700Schasinglulu		CLK_USBO_USBPHY
235*91f16700Schasinglulu		CLK_ADC_CKPER
236*91f16700Schasinglulu		CLK_CEC_LSE
237*91f16700Schasinglulu		CLK_I2C12_HSI
238*91f16700Schasinglulu		CLK_I2C35_HSI
239*91f16700Schasinglulu		CLK_UART1_HSI
240*91f16700Schasinglulu		CLK_UART24_HSI
241*91f16700Schasinglulu		CLK_UART35_HSI
242*91f16700Schasinglulu		CLK_UART6_HSI
243*91f16700Schasinglulu		CLK_UART78_HSI
244*91f16700Schasinglulu		CLK_SPDIF_PLL4P
245*91f16700Schasinglulu		CLK_FDCAN_PLL4R
246*91f16700Schasinglulu		CLK_SAI1_PLL3Q
247*91f16700Schasinglulu		CLK_SAI2_PLL3Q
248*91f16700Schasinglulu		CLK_SAI3_PLL3Q
249*91f16700Schasinglulu		CLK_SAI4_PLL3Q
250*91f16700Schasinglulu		CLK_RNG1_LSI
251*91f16700Schasinglulu		CLK_RNG2_LSI
252*91f16700Schasinglulu		CLK_LPTIM1_PCLK1
253*91f16700Schasinglulu		CLK_LPTIM23_PCLK3
254*91f16700Schasinglulu		CLK_LPTIM45_LSE
255*91f16700Schasinglulu	>;
256*91f16700Schasinglulu
257*91f16700Schasinglulu	/* VCO = 1300.0 MHz => P = 650 (CPU) */
258*91f16700Schasinglulu	pll1: st,pll@0 {
259*91f16700Schasinglulu		compatible = "st,stm32mp1-pll";
260*91f16700Schasinglulu		reg = <0>;
261*91f16700Schasinglulu		cfg = <2 80 0 0 0 PQR(1,0,0)>;
262*91f16700Schasinglulu		frac = <0x800>;
263*91f16700Schasinglulu	};
264*91f16700Schasinglulu
265*91f16700Schasinglulu	/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
266*91f16700Schasinglulu	pll2: st,pll@1 {
267*91f16700Schasinglulu		compatible = "st,stm32mp1-pll";
268*91f16700Schasinglulu		reg = <1>;
269*91f16700Schasinglulu		cfg = <2 65 1 0 0 PQR(1,1,1)>;
270*91f16700Schasinglulu		frac = <0x1400>;
271*91f16700Schasinglulu	};
272*91f16700Schasinglulu
273*91f16700Schasinglulu	/* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
274*91f16700Schasinglulu	pll3: st,pll@2 {
275*91f16700Schasinglulu		compatible = "st,stm32mp1-pll";
276*91f16700Schasinglulu		reg = <2>;
277*91f16700Schasinglulu		cfg = <1 33 1 16 36 PQR(1,1,1)>;
278*91f16700Schasinglulu		frac = <0x1a04>;
279*91f16700Schasinglulu	};
280*91f16700Schasinglulu
281*91f16700Schasinglulu	/* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
282*91f16700Schasinglulu	pll4: st,pll@3 {
283*91f16700Schasinglulu		compatible = "st,stm32mp1-pll";
284*91f16700Schasinglulu		reg = <3>;
285*91f16700Schasinglulu		cfg = <3 98 5 7 7 PQR(1,1,1)>;
286*91f16700Schasinglulu	};
287*91f16700Schasinglulu};
288*91f16700Schasinglulu
289*91f16700Schasinglulu&rng1 {
290*91f16700Schasinglulu	status = "okay";
291*91f16700Schasinglulu};
292*91f16700Schasinglulu
293*91f16700Schasinglulu&rtc {
294*91f16700Schasinglulu	status = "okay";
295*91f16700Schasinglulu};
296*91f16700Schasinglulu
297*91f16700Schasinglulu&sdmmc1 {
298*91f16700Schasinglulu	pinctrl-names = "default";
299*91f16700Schasinglulu	pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>;
300*91f16700Schasinglulu	disable-wp;
301*91f16700Schasinglulu	st,sig-dir;
302*91f16700Schasinglulu	st,neg-edge;
303*91f16700Schasinglulu	st,use-ckin;
304*91f16700Schasinglulu	bus-width = <4>;
305*91f16700Schasinglulu	vmmc-supply = <&vdd_sd>;
306*91f16700Schasinglulu	sd-uhs-sdr12;
307*91f16700Schasinglulu	sd-uhs-sdr25;
308*91f16700Schasinglulu	sd-uhs-sdr50;
309*91f16700Schasinglulu	sd-uhs-ddr50;
310*91f16700Schasinglulu	status = "okay";
311*91f16700Schasinglulu};
312*91f16700Schasinglulu
313*91f16700Schasinglulu&sdmmc2 {
314*91f16700Schasinglulu	pinctrl-names = "default";
315*91f16700Schasinglulu	pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>;
316*91f16700Schasinglulu	non-removable;
317*91f16700Schasinglulu	no-sd;
318*91f16700Schasinglulu	no-sdio;
319*91f16700Schasinglulu	st,neg-edge;
320*91f16700Schasinglulu	bus-width = <8>;
321*91f16700Schasinglulu	vmmc-supply = <&v3v3>;
322*91f16700Schasinglulu	vqmmc-supply = <&vdd>;
323*91f16700Schasinglulu	mmc-ddr-3_3v;
324*91f16700Schasinglulu	status = "okay";
325*91f16700Schasinglulu};
326*91f16700Schasinglulu
327*91f16700Schasinglulu&uart4 {
328*91f16700Schasinglulu	pinctrl-names = "default";
329*91f16700Schasinglulu	pinctrl-0 = <&uart4_pins_a>;
330*91f16700Schasinglulu	status = "okay";
331*91f16700Schasinglulu};
332