1*91f16700Schasinglulu// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause 2*91f16700Schasinglulu/* 3*91f16700Schasinglulu * Copyright (C) 2020, DH electronics - All Rights Reserved 4*91f16700Schasinglulu * 5*91f16700Schasinglulu * STM32MP15xx DHSOM configuration 6*91f16700Schasinglulu * 2x DDR3L 4Gb each, 16-bit, 533MHz, Single Die Package in flyby topology. 7*91f16700Schasinglulu * Reference used W634GU6NB15I from Winbond 8*91f16700Schasinglulu * 9*91f16700Schasinglulu * DDR type / Platform DDR3/3L 10*91f16700Schasinglulu * freq 533MHz 11*91f16700Schasinglulu * width 32 12*91f16700Schasinglulu * datasheet 0 = W634GU6NB15I / DDR3-1333 13*91f16700Schasinglulu * DDR density 8 14*91f16700Schasinglulu * timing mode optimized 15*91f16700Schasinglulu * address mapping : RBC 16*91f16700Schasinglulu * Tc > + 85C : J 17*91f16700Schasinglulu */ 18*91f16700Schasinglulu 19*91f16700Schasinglulu#define DDR_MEM_NAME "DDR3L 32bits 2x4Gb 533MHz" 20*91f16700Schasinglulu#define DDR_MEM_SPEED 533000 21*91f16700Schasinglulu#define DDR_MEM_SIZE 0x40000000 22*91f16700Schasinglulu 23*91f16700Schasinglulu#define DDR_MSTR 0x00040401 24*91f16700Schasinglulu#define DDR_MRCTRL0 0x00000010 25*91f16700Schasinglulu#define DDR_MRCTRL1 0x00000000 26*91f16700Schasinglulu#define DDR_DERATEEN 0x00000000 27*91f16700Schasinglulu#define DDR_DERATEINT 0x00800000 28*91f16700Schasinglulu#define DDR_PWRCTL 0x00000000 29*91f16700Schasinglulu#define DDR_PWRTMG 0x00400010 30*91f16700Schasinglulu#define DDR_HWLPCTL 0x00000000 31*91f16700Schasinglulu#define DDR_RFSHCTL0 0x00210000 32*91f16700Schasinglulu#define DDR_RFSHCTL3 0x00000000 33*91f16700Schasinglulu#define DDR_RFSHTMG 0x0040008B 34*91f16700Schasinglulu#define DDR_CRCPARCTL0 0x00000000 35*91f16700Schasinglulu#define DDR_DRAMTMG0 0x121B1214 36*91f16700Schasinglulu#define DDR_DRAMTMG1 0x000A041C 37*91f16700Schasinglulu#define DDR_DRAMTMG2 0x0608090F 38*91f16700Schasinglulu#define DDR_DRAMTMG3 0x0050400C 39*91f16700Schasinglulu#define DDR_DRAMTMG4 0x08040608 40*91f16700Schasinglulu#define DDR_DRAMTMG5 0x06060403 41*91f16700Schasinglulu#define DDR_DRAMTMG6 0x02020002 42*91f16700Schasinglulu#define DDR_DRAMTMG7 0x00000202 43*91f16700Schasinglulu#define DDR_DRAMTMG8 0x00001005 44*91f16700Schasinglulu#define DDR_DRAMTMG14 0x000000A0 45*91f16700Schasinglulu#define DDR_ZQCTL0 0xC2000040 46*91f16700Schasinglulu#define DDR_DFITMG0 0x02060105 47*91f16700Schasinglulu#define DDR_DFITMG1 0x00000202 48*91f16700Schasinglulu#define DDR_DFILPCFG0 0x07000000 49*91f16700Schasinglulu#define DDR_DFIUPD0 0xC0400003 50*91f16700Schasinglulu#define DDR_DFIUPD1 0x00000000 51*91f16700Schasinglulu#define DDR_DFIUPD2 0x00000000 52*91f16700Schasinglulu#define DDR_DFIPHYMSTR 0x00000000 53*91f16700Schasinglulu#define DDR_ODTCFG 0x06000600 54*91f16700Schasinglulu#define DDR_ODTMAP 0x00000001 55*91f16700Schasinglulu#define DDR_SCHED 0x00000C01 56*91f16700Schasinglulu#define DDR_SCHED1 0x00000000 57*91f16700Schasinglulu#define DDR_PERFHPR1 0x01000001 58*91f16700Schasinglulu#define DDR_PERFLPR1 0x08000200 59*91f16700Schasinglulu#define DDR_PERFWR1 0x08000400 60*91f16700Schasinglulu#define DDR_DBG0 0x00000000 61*91f16700Schasinglulu#define DDR_DBG1 0x00000000 62*91f16700Schasinglulu#define DDR_DBGCMD 0x00000000 63*91f16700Schasinglulu#define DDR_POISONCFG 0x00000000 64*91f16700Schasinglulu#define DDR_PCCFG 0x00000010 65*91f16700Schasinglulu#define DDR_PCFGR_0 0x00010000 66*91f16700Schasinglulu#define DDR_PCFGW_0 0x00000000 67*91f16700Schasinglulu#define DDR_PCFGQOS0_0 0x02100C03 68*91f16700Schasinglulu#define DDR_PCFGQOS1_0 0x00800100 69*91f16700Schasinglulu#define DDR_PCFGWQOS0_0 0x01100C03 70*91f16700Schasinglulu#define DDR_PCFGWQOS1_0 0x01000200 71*91f16700Schasinglulu#define DDR_PCFGR_1 0x00010000 72*91f16700Schasinglulu#define DDR_PCFGW_1 0x00000000 73*91f16700Schasinglulu#define DDR_PCFGQOS0_1 0x02100C03 74*91f16700Schasinglulu#define DDR_PCFGQOS1_1 0x00800040 75*91f16700Schasinglulu#define DDR_PCFGWQOS0_1 0x01100C03 76*91f16700Schasinglulu#define DDR_PCFGWQOS1_1 0x01000200 77*91f16700Schasinglulu#define DDR_ADDRMAP1 0x00080808 78*91f16700Schasinglulu#define DDR_ADDRMAP2 0x00000000 79*91f16700Schasinglulu#define DDR_ADDRMAP3 0x00000000 80*91f16700Schasinglulu#define DDR_ADDRMAP4 0x00001F1F 81*91f16700Schasinglulu#define DDR_ADDRMAP5 0x07070707 82*91f16700Schasinglulu#define DDR_ADDRMAP6 0x0F070707 83*91f16700Schasinglulu#define DDR_ADDRMAP9 0x00000000 84*91f16700Schasinglulu#define DDR_ADDRMAP10 0x00000000 85*91f16700Schasinglulu#define DDR_ADDRMAP11 0x00000000 86*91f16700Schasinglulu#define DDR_PGCR 0x01442E02 87*91f16700Schasinglulu#define DDR_PTR0 0x0022AA5B 88*91f16700Schasinglulu#define DDR_PTR1 0x04841104 89*91f16700Schasinglulu#define DDR_PTR2 0x042DA068 90*91f16700Schasinglulu#define DDR_ACIOCR 0x10400812 91*91f16700Schasinglulu#define DDR_DXCCR 0x00000C40 92*91f16700Schasinglulu#define DDR_DSGCR 0xF200011F 93*91f16700Schasinglulu#define DDR_DCR 0x0000000B 94*91f16700Schasinglulu#define DDR_DTPR0 0x38D488D0 95*91f16700Schasinglulu#define DDR_DTPR1 0x098B00D8 96*91f16700Schasinglulu#define DDR_DTPR2 0x10023600 97*91f16700Schasinglulu#define DDR_MR0 0x00000840 98*91f16700Schasinglulu#define DDR_MR1 0x00000000 99*91f16700Schasinglulu#define DDR_MR2 0x00000248 100*91f16700Schasinglulu#define DDR_MR3 0x00000000 101*91f16700Schasinglulu#define DDR_ODTCR 0x00010000 102*91f16700Schasinglulu#define DDR_ZQ0CR1 0x00000038 103*91f16700Schasinglulu#define DDR_DX0GCR 0x0000CE81 104*91f16700Schasinglulu#define DDR_DX1GCR 0x0000CE81 105*91f16700Schasinglulu#define DDR_DX2GCR 0x0000CE81 106*91f16700Schasinglulu#define DDR_DX3GCR 0x0000CE81 107*91f16700Schasinglulu 108*91f16700Schasinglulu#include "stm32mp15-ddr.dtsi" 109