1*91f16700Schasinglulu// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2*91f16700Schasinglulu/* 3*91f16700Schasinglulu * Copyright (C) STMicroelectronics 2022 - All Rights Reserved 4*91f16700Schasinglulu * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu/dts-v1/; 8*91f16700Schasinglulu 9*91f16700Schasinglulu#include <dt-bindings/clock/stm32mp13-clksrc.h> 10*91f16700Schasinglulu#include "stm32mp135.dtsi" 11*91f16700Schasinglulu#include "stm32mp13xf.dtsi" 12*91f16700Schasinglulu#include "stm32mp13-ddr3-1x4Gb-1066-binF.dtsi" 13*91f16700Schasinglulu#include "stm32mp13-pinctrl.dtsi" 14*91f16700Schasinglulu 15*91f16700Schasinglulu/ { 16*91f16700Schasinglulu model = "STMicroelectronics STM32MP135F-DK Discovery Board"; 17*91f16700Schasinglulu compatible = "st,stm32mp135f-dk", "st,stm32mp135"; 18*91f16700Schasinglulu 19*91f16700Schasinglulu aliases { 20*91f16700Schasinglulu serial0 = &uart4; 21*91f16700Schasinglulu serial1 = &usart1; 22*91f16700Schasinglulu serial2 = &uart8; 23*91f16700Schasinglulu serial3 = &usart2; 24*91f16700Schasinglulu }; 25*91f16700Schasinglulu 26*91f16700Schasinglulu chosen { 27*91f16700Schasinglulu stdout-path = "serial0:115200n8"; 28*91f16700Schasinglulu }; 29*91f16700Schasinglulu 30*91f16700Schasinglulu memory@c0000000 { 31*91f16700Schasinglulu device_type = "memory"; 32*91f16700Schasinglulu reg = <0xc0000000 0x20000000>; 33*91f16700Schasinglulu }; 34*91f16700Schasinglulu 35*91f16700Schasinglulu vin: vin { 36*91f16700Schasinglulu compatible = "regulator-fixed"; 37*91f16700Schasinglulu regulator-name = "vin"; 38*91f16700Schasinglulu regulator-min-microvolt = <5000000>; 39*91f16700Schasinglulu regulator-max-microvolt = <5000000>; 40*91f16700Schasinglulu regulator-always-on; 41*91f16700Schasinglulu }; 42*91f16700Schasinglulu 43*91f16700Schasinglulu v3v3_ao: v3v3_ao { 44*91f16700Schasinglulu compatible = "regulator-fixed"; 45*91f16700Schasinglulu regulator-name = "v3v3_ao"; 46*91f16700Schasinglulu regulator-min-microvolt = <3300000>; 47*91f16700Schasinglulu regulator-max-microvolt = <3300000>; 48*91f16700Schasinglulu regulator-always-on; 49*91f16700Schasinglulu }; 50*91f16700Schasinglulu}; 51*91f16700Schasinglulu 52*91f16700Schasinglulu&bsec { 53*91f16700Schasinglulu board_id: board_id@f0 { 54*91f16700Schasinglulu reg = <0xf0 0x4>; 55*91f16700Schasinglulu st,non-secure-otp; 56*91f16700Schasinglulu }; 57*91f16700Schasinglulu}; 58*91f16700Schasinglulu 59*91f16700Schasinglulu&cpu0 { 60*91f16700Schasinglulu cpu-supply = <&vddcpu>; 61*91f16700Schasinglulu}; 62*91f16700Schasinglulu 63*91f16700Schasinglulu&hash { 64*91f16700Schasinglulu status = "okay"; 65*91f16700Schasinglulu}; 66*91f16700Schasinglulu 67*91f16700Schasinglulu&i2c4 { 68*91f16700Schasinglulu pinctrl-names = "default"; 69*91f16700Schasinglulu pinctrl-0 = <&i2c4_pins_a>; 70*91f16700Schasinglulu i2c-scl-rising-time-ns = <185>; 71*91f16700Schasinglulu i2c-scl-falling-time-ns = <20>; 72*91f16700Schasinglulu clock-frequency = <400000>; 73*91f16700Schasinglulu status = "disabled"; 74*91f16700Schasinglulu secure-status = "okay"; 75*91f16700Schasinglulu 76*91f16700Schasinglulu pmic: stpmic@33 { 77*91f16700Schasinglulu compatible = "st,stpmic1"; 78*91f16700Schasinglulu reg = <0x33>; 79*91f16700Schasinglulu 80*91f16700Schasinglulu status = "disabled"; 81*91f16700Schasinglulu secure-status = "okay"; 82*91f16700Schasinglulu 83*91f16700Schasinglulu regulators { 84*91f16700Schasinglulu compatible = "st,stpmic1-regulators"; 85*91f16700Schasinglulu buck1-supply = <&vin>; 86*91f16700Schasinglulu buck2-supply = <&vin>; 87*91f16700Schasinglulu buck3-supply = <&vin>; 88*91f16700Schasinglulu buck4-supply = <&vin>; 89*91f16700Schasinglulu ldo1-supply = <&vin>; 90*91f16700Schasinglulu ldo4-supply = <&vin>; 91*91f16700Schasinglulu ldo5-supply = <&vin>; 92*91f16700Schasinglulu ldo6-supply = <&vin>; 93*91f16700Schasinglulu vref_ddr-supply = <&vin>; 94*91f16700Schasinglulu pwr_sw1-supply = <&bst_out>; 95*91f16700Schasinglulu pwr_sw2-supply = <&v3v3_ao>; 96*91f16700Schasinglulu 97*91f16700Schasinglulu vddcpu: buck1 { 98*91f16700Schasinglulu regulator-name = "vddcpu"; 99*91f16700Schasinglulu regulator-min-microvolt = <1250000>; 100*91f16700Schasinglulu regulator-max-microvolt = <1250000>; 101*91f16700Schasinglulu regulator-always-on; 102*91f16700Schasinglulu regulator-over-current-protection; 103*91f16700Schasinglulu }; 104*91f16700Schasinglulu 105*91f16700Schasinglulu vdd_ddr: buck2 { 106*91f16700Schasinglulu regulator-name = "vdd_ddr"; 107*91f16700Schasinglulu regulator-min-microvolt = <1350000>; 108*91f16700Schasinglulu regulator-max-microvolt = <1350000>; 109*91f16700Schasinglulu regulator-always-on; 110*91f16700Schasinglulu regulator-over-current-protection; 111*91f16700Schasinglulu }; 112*91f16700Schasinglulu 113*91f16700Schasinglulu vdd: buck3 { 114*91f16700Schasinglulu regulator-name = "vdd"; 115*91f16700Schasinglulu regulator-min-microvolt = <3300000>; 116*91f16700Schasinglulu regulator-max-microvolt = <3300000>; 117*91f16700Schasinglulu regulator-always-on; 118*91f16700Schasinglulu st,mask-reset; 119*91f16700Schasinglulu regulator-over-current-protection; 120*91f16700Schasinglulu }; 121*91f16700Schasinglulu 122*91f16700Schasinglulu vddcore: buck4 { 123*91f16700Schasinglulu regulator-name = "vddcore"; 124*91f16700Schasinglulu regulator-min-microvolt = <1250000>; 125*91f16700Schasinglulu regulator-max-microvolt = <1250000>; 126*91f16700Schasinglulu regulator-always-on; 127*91f16700Schasinglulu regulator-over-current-protection; 128*91f16700Schasinglulu }; 129*91f16700Schasinglulu 130*91f16700Schasinglulu vdd_adc: ldo1 { 131*91f16700Schasinglulu regulator-name = "vdd_adc"; 132*91f16700Schasinglulu regulator-min-microvolt = <3300000>; 133*91f16700Schasinglulu regulator-max-microvolt = <3300000>; 134*91f16700Schasinglulu }; 135*91f16700Schasinglulu 136*91f16700Schasinglulu vdd_usb: ldo4 { 137*91f16700Schasinglulu regulator-name = "vdd_usb"; 138*91f16700Schasinglulu regulator-min-microvolt = <3300000>; 139*91f16700Schasinglulu regulator-max-microvolt = <3300000>; 140*91f16700Schasinglulu }; 141*91f16700Schasinglulu 142*91f16700Schasinglulu vdd_sd: ldo5 { 143*91f16700Schasinglulu regulator-name = "vdd_sd"; 144*91f16700Schasinglulu regulator-min-microvolt = <3300000>; 145*91f16700Schasinglulu regulator-max-microvolt = <3300000>; 146*91f16700Schasinglulu regulator-boot-on; 147*91f16700Schasinglulu }; 148*91f16700Schasinglulu 149*91f16700Schasinglulu v1v8_periph: ldo6 { 150*91f16700Schasinglulu regulator-name = "v1v8_periph"; 151*91f16700Schasinglulu regulator-min-microvolt = <1800000>; 152*91f16700Schasinglulu regulator-max-microvolt = <1800000>; 153*91f16700Schasinglulu }; 154*91f16700Schasinglulu 155*91f16700Schasinglulu vref_ddr: vref_ddr { 156*91f16700Schasinglulu regulator-name = "vref_ddr"; 157*91f16700Schasinglulu regulator-always-on; 158*91f16700Schasinglulu }; 159*91f16700Schasinglulu 160*91f16700Schasinglulu bst_out: boost { 161*91f16700Schasinglulu regulator-name = "bst_out"; 162*91f16700Schasinglulu }; 163*91f16700Schasinglulu 164*91f16700Schasinglulu v3v3_sw: pwr_sw2 { 165*91f16700Schasinglulu regulator-name = "v3v3_sw"; 166*91f16700Schasinglulu regulator-active-discharge = <1>; 167*91f16700Schasinglulu regulator-always-on; 168*91f16700Schasinglulu }; 169*91f16700Schasinglulu }; 170*91f16700Schasinglulu }; 171*91f16700Schasinglulu}; 172*91f16700Schasinglulu 173*91f16700Schasinglulu&iwdg2 { 174*91f16700Schasinglulu timeout-sec = <32>; 175*91f16700Schasinglulu status = "okay"; 176*91f16700Schasinglulu}; 177*91f16700Schasinglulu 178*91f16700Schasinglulu&pka { 179*91f16700Schasinglulu status = "okay"; 180*91f16700Schasinglulu}; 181*91f16700Schasinglulu 182*91f16700Schasinglulu&pwr_regulators { 183*91f16700Schasinglulu vdd-supply = <&vdd>; 184*91f16700Schasinglulu vdd_3v3_usbfs-supply = <&vdd_usb>; 185*91f16700Schasinglulu}; 186*91f16700Schasinglulu 187*91f16700Schasinglulu&rcc { 188*91f16700Schasinglulu st,clksrc = < 189*91f16700Schasinglulu CLK_MPU_PLL1P 190*91f16700Schasinglulu CLK_AXI_PLL2P 191*91f16700Schasinglulu CLK_MLAHBS_PLL3 192*91f16700Schasinglulu CLK_CKPER_HSE 193*91f16700Schasinglulu CLK_RTC_LSE 194*91f16700Schasinglulu CLK_SDMMC1_PLL4P 195*91f16700Schasinglulu CLK_SDMMC2_PLL4P 196*91f16700Schasinglulu CLK_STGEN_HSE 197*91f16700Schasinglulu CLK_USBPHY_HSE 198*91f16700Schasinglulu CLK_I2C4_HSI 199*91f16700Schasinglulu CLK_USBO_USBPHY 200*91f16700Schasinglulu CLK_I2C12_HSI 201*91f16700Schasinglulu CLK_UART2_HSI 202*91f16700Schasinglulu CLK_UART4_HSI 203*91f16700Schasinglulu CLK_SAES_AXI 204*91f16700Schasinglulu >; 205*91f16700Schasinglulu 206*91f16700Schasinglulu st,clkdiv = < 207*91f16700Schasinglulu DIV(DIV_AXI, 0) 208*91f16700Schasinglulu DIV(DIV_MLAHB, 0) 209*91f16700Schasinglulu DIV(DIV_APB1, 1) 210*91f16700Schasinglulu DIV(DIV_APB2, 1) 211*91f16700Schasinglulu DIV(DIV_APB3, 1) 212*91f16700Schasinglulu DIV(DIV_APB4, 1) 213*91f16700Schasinglulu DIV(DIV_APB5, 2) 214*91f16700Schasinglulu DIV(DIV_APB6, 1) 215*91f16700Schasinglulu DIV(DIV_RTC, 0) 216*91f16700Schasinglulu >; 217*91f16700Schasinglulu 218*91f16700Schasinglulu st,pll_vco { 219*91f16700Schasinglulu pll1_vco_1300Mhz: pll1-vco-1300Mhz { 220*91f16700Schasinglulu src = < CLK_PLL12_HSE >; 221*91f16700Schasinglulu divmn = < 2 80 >; 222*91f16700Schasinglulu frac = < 0x800 >; 223*91f16700Schasinglulu }; 224*91f16700Schasinglulu 225*91f16700Schasinglulu pll2_vco_1066Mhz: pll2-vco-1066Mhz { 226*91f16700Schasinglulu src = <CLK_PLL12_HSE>; 227*91f16700Schasinglulu divmn = <2 65>; 228*91f16700Schasinglulu frac = <0x1400>; 229*91f16700Schasinglulu }; 230*91f16700Schasinglulu 231*91f16700Schasinglulu pll3_vco_417Mhz: pll3-vco-417Mhz { 232*91f16700Schasinglulu src = <CLK_PLL3_HSE>; 233*91f16700Schasinglulu divmn = <1 33>; 234*91f16700Schasinglulu frac = <0x1a04>; 235*91f16700Schasinglulu }; 236*91f16700Schasinglulu 237*91f16700Schasinglulu pll4_vco_600Mhz: pll4-vco-600Mhz { 238*91f16700Schasinglulu src = <CLK_PLL4_HSE>; 239*91f16700Schasinglulu divmn = <1 49>; 240*91f16700Schasinglulu }; 241*91f16700Schasinglulu }; 242*91f16700Schasinglulu 243*91f16700Schasinglulu /* VCO = 1300.0 MHz => P = 650 (CPU) */ 244*91f16700Schasinglulu pll1:st,pll@0 { 245*91f16700Schasinglulu compatible = "st,stm32mp1-pll"; 246*91f16700Schasinglulu reg = <0>; 247*91f16700Schasinglulu 248*91f16700Schasinglulu st,pll = < &pll1_cfg1 >; 249*91f16700Schasinglulu 250*91f16700Schasinglulu pll1_cfg1: pll1_cfg1 { 251*91f16700Schasinglulu st,pll_vco = < &pll1_vco_1300Mhz >; 252*91f16700Schasinglulu st,pll_div_pqr = < 0 1 1 >; 253*91f16700Schasinglulu }; 254*91f16700Schasinglulu }; 255*91f16700Schasinglulu 256*91f16700Schasinglulu /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 266, R = 533 (DDR) */ 257*91f16700Schasinglulu pll2:st,pll@1 { 258*91f16700Schasinglulu compatible = "st,stm32mp1-pll"; 259*91f16700Schasinglulu reg = <1>; 260*91f16700Schasinglulu 261*91f16700Schasinglulu st,pll = <&pll2_cfg1>; 262*91f16700Schasinglulu 263*91f16700Schasinglulu pll2_cfg1: pll2_cfg1 { 264*91f16700Schasinglulu st,pll_vco = <&pll2_vco_1066Mhz>; 265*91f16700Schasinglulu st,pll_div_pqr = <1 1 0>; 266*91f16700Schasinglulu }; 267*91f16700Schasinglulu }; 268*91f16700Schasinglulu 269*91f16700Schasinglulu /* VCO = 417.8 MHz => P = 209, Q = 24, R = 209 */ 270*91f16700Schasinglulu pll3:st,pll@2 { 271*91f16700Schasinglulu compatible = "st,stm32mp1-pll"; 272*91f16700Schasinglulu reg = <2>; 273*91f16700Schasinglulu 274*91f16700Schasinglulu st,pll = <&pll3_cfg1>; 275*91f16700Schasinglulu 276*91f16700Schasinglulu pll3_cfg1: pll3_cfg1 { 277*91f16700Schasinglulu st,pll_vco = <&pll3_vco_417Mhz>; 278*91f16700Schasinglulu st,pll_div_pqr = <1 16 1>; 279*91f16700Schasinglulu }; 280*91f16700Schasinglulu }; 281*91f16700Schasinglulu 282*91f16700Schasinglulu /* VCO = 600.0 MHz => P = 50, Q = 10, R = 100 */ 283*91f16700Schasinglulu pll4:st,pll@3 { 284*91f16700Schasinglulu compatible = "st,stm32mp1-pll"; 285*91f16700Schasinglulu reg = <3>; 286*91f16700Schasinglulu 287*91f16700Schasinglulu st,pll = <&pll4_cfg1>; 288*91f16700Schasinglulu 289*91f16700Schasinglulu pll4_cfg1: pll4_cfg1 { 290*91f16700Schasinglulu st,pll_vco = <&pll4_vco_600Mhz>; 291*91f16700Schasinglulu st,pll_div_pqr = <11 59 5>; 292*91f16700Schasinglulu }; 293*91f16700Schasinglulu }; 294*91f16700Schasinglulu}; 295*91f16700Schasinglulu 296*91f16700Schasinglulu&rng { 297*91f16700Schasinglulu status = "okay"; 298*91f16700Schasinglulu}; 299*91f16700Schasinglulu 300*91f16700Schasinglulu&saes { 301*91f16700Schasinglulu status = "okay"; 302*91f16700Schasinglulu}; 303*91f16700Schasinglulu 304*91f16700Schasinglulu&sdmmc1 { 305*91f16700Schasinglulu pinctrl-names = "default"; 306*91f16700Schasinglulu pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_clk_pins_a>; 307*91f16700Schasinglulu disable-wp; 308*91f16700Schasinglulu st,neg-edge; 309*91f16700Schasinglulu bus-width = <4>; 310*91f16700Schasinglulu vmmc-supply = <&vdd_sd>; 311*91f16700Schasinglulu status = "okay"; 312*91f16700Schasinglulu}; 313*91f16700Schasinglulu 314*91f16700Schasinglulu&uart4 { 315*91f16700Schasinglulu pinctrl-names = "default"; 316*91f16700Schasinglulu pinctrl-0 = <&uart4_pins_a>; 317*91f16700Schasinglulu status = "okay"; 318*91f16700Schasinglulu}; 319*91f16700Schasinglulu 320*91f16700Schasinglulu&uart8 { 321*91f16700Schasinglulu pinctrl-names = "default"; 322*91f16700Schasinglulu pinctrl-0 = <&uart8_pins_a>; 323*91f16700Schasinglulu status = "disabled"; 324*91f16700Schasinglulu}; 325*91f16700Schasinglulu 326*91f16700Schasinglulu&usart1 { 327*91f16700Schasinglulu pinctrl-names = "default"; 328*91f16700Schasinglulu pinctrl-0 = <&usart1_pins_a>; 329*91f16700Schasinglulu uart-has-rtscts; 330*91f16700Schasinglulu status = "disabled"; 331*91f16700Schasinglulu}; 332