xref: /arm-trusted-firmware/fdts/fvp-foundation-gicv2-psci.dts (revision 91f16700b400a8c0651d24a598fc48ee2997a0d7)
1*91f16700Schasinglulu/*
2*91f16700Schasinglulu * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved.
3*91f16700Schasinglulu *
4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause
5*91f16700Schasinglulu */
6*91f16700Schasinglulu
7*91f16700Schasinglulu/* Configuration: 1 cluster with up to 4 CPUs */
8*91f16700Schasinglulu
9*91f16700Schasinglulu/dts-v1/;
10*91f16700Schasinglulu
11*91f16700Schasinglulu#define	AFF
12*91f16700Schasinglulu#define	CLUSTER_COUNT	1
13*91f16700Schasinglulu
14*91f16700Schasinglulu#include <dt-bindings/interrupt-controller/arm-gic.h>
15*91f16700Schasinglulu#include "fvp-defs.dtsi"
16*91f16700Schasinglulu
17*91f16700Schasinglulu/memreserve/ 0x80000000 0x00010000;
18*91f16700Schasinglulu
19*91f16700Schasinglulu/ {
20*91f16700Schasinglulu};
21*91f16700Schasinglulu
22*91f16700Schasinglulu/ {
23*91f16700Schasinglulu	model = "FVP Foundation";
24*91f16700Schasinglulu	compatible = "arm,fvp-base", "arm,vexpress";
25*91f16700Schasinglulu	interrupt-parent = <&gic>;
26*91f16700Schasinglulu	#address-cells = <2>;
27*91f16700Schasinglulu	#size-cells = <2>;
28*91f16700Schasinglulu
29*91f16700Schasinglulu	chosen { };
30*91f16700Schasinglulu
31*91f16700Schasinglulu	aliases {
32*91f16700Schasinglulu		serial0 = &v2m_serial0;
33*91f16700Schasinglulu		serial1 = &v2m_serial1;
34*91f16700Schasinglulu		serial2 = &v2m_serial2;
35*91f16700Schasinglulu		serial3 = &v2m_serial3;
36*91f16700Schasinglulu	};
37*91f16700Schasinglulu
38*91f16700Schasinglulu	psci {
39*91f16700Schasinglulu		compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
40*91f16700Schasinglulu		method = "smc";
41*91f16700Schasinglulu		cpu_suspend = <0xc4000001>;
42*91f16700Schasinglulu		cpu_off = <0x84000002>;
43*91f16700Schasinglulu		cpu_on = <0xc4000003>;
44*91f16700Schasinglulu		sys_poweroff = <0x84000008>;
45*91f16700Schasinglulu		sys_reset = <0x84000009>;
46*91f16700Schasinglulu		max-pwr-lvl = <2>;
47*91f16700Schasinglulu	};
48*91f16700Schasinglulu
49*91f16700Schasinglulu	cpus {
50*91f16700Schasinglulu		#address-cells = <2>;
51*91f16700Schasinglulu		#size-cells = <0>;
52*91f16700Schasinglulu
53*91f16700Schasinglulu		CPU_MAP
54*91f16700Schasinglulu
55*91f16700Schasinglulu		idle-states {
56*91f16700Schasinglulu			entry-method = "arm,psci";
57*91f16700Schasinglulu
58*91f16700Schasinglulu			CPU_SLEEP_0: cpu-sleep-0 {
59*91f16700Schasinglulu				compatible = "arm,idle-state";
60*91f16700Schasinglulu				local-timer-stop;
61*91f16700Schasinglulu				arm,psci-suspend-param = <0x0010000>;
62*91f16700Schasinglulu				entry-latency-us = <40>;
63*91f16700Schasinglulu				exit-latency-us = <100>;
64*91f16700Schasinglulu				min-residency-us = <150>;
65*91f16700Schasinglulu			};
66*91f16700Schasinglulu
67*91f16700Schasinglulu			CLUSTER_SLEEP_0: cluster-sleep-0 {
68*91f16700Schasinglulu				compatible = "arm,idle-state";
69*91f16700Schasinglulu				local-timer-stop;
70*91f16700Schasinglulu				arm,psci-suspend-param = <0x1010000>;
71*91f16700Schasinglulu				entry-latency-us = <500>;
72*91f16700Schasinglulu				exit-latency-us = <1000>;
73*91f16700Schasinglulu				min-residency-us = <2500>;
74*91f16700Schasinglulu			};
75*91f16700Schasinglulu		};
76*91f16700Schasinglulu
77*91f16700Schasinglulu		CPUS
78*91f16700Schasinglulu
79*91f16700Schasinglulu		L2_0: l2-cache0 {
80*91f16700Schasinglulu			compatible = "cache";
81*91f16700Schasinglulu		};
82*91f16700Schasinglulu	};
83*91f16700Schasinglulu
84*91f16700Schasinglulu	memory@80000000 {
85*91f16700Schasinglulu		device_type = "memory";
86*91f16700Schasinglulu		reg = <0x00000000 0x80000000 0 0x7F000000>,
87*91f16700Schasinglulu		      <0x00000008 0x80000000 0 0x80000000>;
88*91f16700Schasinglulu	};
89*91f16700Schasinglulu
90*91f16700Schasinglulu	gic: interrupt-controller@2f000000 {
91*91f16700Schasinglulu		compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
92*91f16700Schasinglulu		#interrupt-cells = <3>;
93*91f16700Schasinglulu		#address-cells = <0>;
94*91f16700Schasinglulu		interrupt-controller;
95*91f16700Schasinglulu		reg = <0x0 0x2f000000 0 0x10000>,
96*91f16700Schasinglulu		      <0x0 0x2c000000 0 0x2000>,
97*91f16700Schasinglulu		      <0x0 0x2c010000 0 0x2000>,
98*91f16700Schasinglulu		      <0x0 0x2c02F000 0 0x2000>;
99*91f16700Schasinglulu		interrupts = <1 9 0xf04>;
100*91f16700Schasinglulu	};
101*91f16700Schasinglulu
102*91f16700Schasinglulu	timer {
103*91f16700Schasinglulu		compatible = "arm,armv8-timer";
104*91f16700Schasinglulu		interrupts = <GIC_PPI 13
105*91f16700Schasinglulu				(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
106*91f16700Schasinglulu			     <GIC_PPI 14
107*91f16700Schasinglulu				(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
108*91f16700Schasinglulu			     <GIC_PPI 11
109*91f16700Schasinglulu				(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
110*91f16700Schasinglulu			     <GIC_PPI 10
111*91f16700Schasinglulu				(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
112*91f16700Schasinglulu		clock-frequency = <100000000>;
113*91f16700Schasinglulu	};
114*91f16700Schasinglulu
115*91f16700Schasinglulu	timer@2a810000 {
116*91f16700Schasinglulu			compatible = "arm,armv7-timer-mem";
117*91f16700Schasinglulu			reg = <0x0 0x2a810000 0x0 0x10000>;
118*91f16700Schasinglulu			clock-frequency = <100000000>;
119*91f16700Schasinglulu			#address-cells = <2>;
120*91f16700Schasinglulu			#size-cells = <2>;
121*91f16700Schasinglulu			ranges;
122*91f16700Schasinglulu			frame@2a830000 {
123*91f16700Schasinglulu				frame-number = <1>;
124*91f16700Schasinglulu				interrupts = <0 26 4>;
125*91f16700Schasinglulu				reg = <0x0 0x2a830000 0x0 0x10000>;
126*91f16700Schasinglulu			};
127*91f16700Schasinglulu	};
128*91f16700Schasinglulu
129*91f16700Schasinglulu	pmu {
130*91f16700Schasinglulu		compatible = "arm,armv8-pmuv3";
131*91f16700Schasinglulu		interrupts = <0 60 4>,
132*91f16700Schasinglulu			     <0 61 4>,
133*91f16700Schasinglulu			     <0 62 4>,
134*91f16700Schasinglulu			     <0 63 4>;
135*91f16700Schasinglulu	};
136*91f16700Schasinglulu
137*91f16700Schasinglulu	smb {
138*91f16700Schasinglulu		compatible = "simple-bus";
139*91f16700Schasinglulu
140*91f16700Schasinglulu		#address-cells = <2>;
141*91f16700Schasinglulu		#size-cells = <1>;
142*91f16700Schasinglulu		ranges = <0 0 0 0x08000000 0x04000000>,
143*91f16700Schasinglulu			 <1 0 0 0x14000000 0x04000000>,
144*91f16700Schasinglulu			 <2 0 0 0x18000000 0x04000000>,
145*91f16700Schasinglulu			 <3 0 0 0x1c000000 0x04000000>,
146*91f16700Schasinglulu			 <4 0 0 0x0c000000 0x04000000>,
147*91f16700Schasinglulu			 <5 0 0 0x10000000 0x04000000>;
148*91f16700Schasinglulu
149*91f16700Schasinglulu		#include "fvp-foundation-motherboard.dtsi"
150*91f16700Schasinglulu	};
151*91f16700Schasinglulu};
152