1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2017-2022, STMicroelectronics - All Rights Reserved 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #include <drivers/st/stm32mp1_ddr_helpers.h> 8*91f16700Schasinglulu #include <lib/mmio.h> 9*91f16700Schasinglulu 10*91f16700Schasinglulu #include <platform_def.h> 11*91f16700Schasinglulu 12*91f16700Schasinglulu void ddr_enable_clock(void) 13*91f16700Schasinglulu { 14*91f16700Schasinglulu stm32mp1_clk_rcc_regs_lock(); 15*91f16700Schasinglulu 16*91f16700Schasinglulu mmio_setbits_32(stm32mp_rcc_base() + RCC_DDRITFCR, 17*91f16700Schasinglulu RCC_DDRITFCR_DDRC1EN | 18*91f16700Schasinglulu #if STM32MP_DDR_DUAL_AXI_PORT 19*91f16700Schasinglulu RCC_DDRITFCR_DDRC2EN | 20*91f16700Schasinglulu #endif 21*91f16700Schasinglulu RCC_DDRITFCR_DDRPHYCEN | 22*91f16700Schasinglulu RCC_DDRITFCR_DDRPHYCAPBEN | 23*91f16700Schasinglulu RCC_DDRITFCR_DDRCAPBEN); 24*91f16700Schasinglulu 25*91f16700Schasinglulu stm32mp1_clk_rcc_regs_unlock(); 26*91f16700Schasinglulu } 27