1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #include <stdint.h> 8*91f16700Schasinglulu 9*91f16700Schasinglulu #include <common/debug.h> 10*91f16700Schasinglulu 11*91f16700Schasinglulu #include "../qos_common.h" 12*91f16700Schasinglulu #include "../qos_reg.h" 13*91f16700Schasinglulu #include "qos_init_h3_v10.h" 14*91f16700Schasinglulu 15*91f16700Schasinglulu #define RCAR_QOS_VERSION "rev.0.36" 16*91f16700Schasinglulu 17*91f16700Schasinglulu #include "qos_init_h3_v10_mstat.h" 18*91f16700Schasinglulu 19*91f16700Schasinglulu void qos_init_h3_v10(void) 20*91f16700Schasinglulu { 21*91f16700Schasinglulu /* DRAM Split Address mapping */ 22*91f16700Schasinglulu #if (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH) || \ 23*91f16700Schasinglulu (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_AUTO) 24*91f16700Schasinglulu NOTICE("BL2: DRAM Split is 4ch\n"); 25*91f16700Schasinglulu io_write_32(AXI_ADSPLCR0, ADSPLCR0_ADRMODE_DEFAULT 26*91f16700Schasinglulu | ADSPLCR0_SPLITSEL(0xFFU) 27*91f16700Schasinglulu | ADSPLCR0_AREA(0x1BU) 28*91f16700Schasinglulu | ADSPLCR0_SWP); 29*91f16700Schasinglulu io_write_32(AXI_ADSPLCR1, 0x00000000U); 30*91f16700Schasinglulu io_write_32(AXI_ADSPLCR2, 0xA8A90000U); 31*91f16700Schasinglulu io_write_32(AXI_ADSPLCR3, 0x00000000U); 32*91f16700Schasinglulu #elif RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH 33*91f16700Schasinglulu NOTICE("BL2: DRAM Split is 2ch\n"); 34*91f16700Schasinglulu io_write_32(AXI_ADSPLCR0, 0x00000000U); 35*91f16700Schasinglulu io_write_32(AXI_ADSPLCR1, ADSPLCR0_ADRMODE_DEFAULT 36*91f16700Schasinglulu | ADSPLCR0_SPLITSEL(0xFFU) 37*91f16700Schasinglulu | ADSPLCR0_AREA(0x1BU) 38*91f16700Schasinglulu | ADSPLCR0_SWP); 39*91f16700Schasinglulu io_write_32(AXI_ADSPLCR2, 0x00000000U); 40*91f16700Schasinglulu io_write_32(AXI_ADSPLCR3, 0x00000000U); 41*91f16700Schasinglulu #else 42*91f16700Schasinglulu NOTICE("BL2: DRAM Split is OFF\n"); 43*91f16700Schasinglulu #endif 44*91f16700Schasinglulu 45*91f16700Schasinglulu #if !(RCAR_QOS_TYPE == RCAR_QOS_NONE) 46*91f16700Schasinglulu #if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT 47*91f16700Schasinglulu NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION); 48*91f16700Schasinglulu #endif 49*91f16700Schasinglulu 50*91f16700Schasinglulu /* AR Cache setting */ 51*91f16700Schasinglulu io_write_32(0xE67D1000U, 0x00000100U); 52*91f16700Schasinglulu io_write_32(0xE67D1008U, 0x00000100U); 53*91f16700Schasinglulu 54*91f16700Schasinglulu /* Resource Alloc setting */ 55*91f16700Schasinglulu io_write_32(QOSCTRL_RAS, 0x00000040U); 56*91f16700Schasinglulu io_write_32(QOSCTRL_FIXTH, 0x000F0005U); 57*91f16700Schasinglulu io_write_32(QOSCTRL_REGGD, 0x00000004U); 58*91f16700Schasinglulu io_write_64(QOSCTRL_DANN, 0x0202000004040404UL); 59*91f16700Schasinglulu io_write_32(QOSCTRL_DANT, 0x003C1110U); 60*91f16700Schasinglulu io_write_32(QOSCTRL_EC, 0x00080001U); /* need for H3 v1.* */ 61*91f16700Schasinglulu io_write_64(QOSCTRL_EMS, 0x0000000000000000UL); 62*91f16700Schasinglulu io_write_32(QOSCTRL_INSFC, 0xC7840001U); 63*91f16700Schasinglulu io_write_32(QOSCTRL_BERR, 0x00000000U); 64*91f16700Schasinglulu 65*91f16700Schasinglulu /* QOSBW setting */ 66*91f16700Schasinglulu io_write_32(QOSCTRL_SL_INIT, 67*91f16700Schasinglulu SL_INIT_REFFSSLOT | SL_INIT_SLOTSSLOT | SL_INIT_SSLOTCLK); 68*91f16700Schasinglulu io_write_32(QOSCTRL_REF_ARS, 0x00330000U); 69*91f16700Schasinglulu 70*91f16700Schasinglulu /* QOSBW SRAM setting */ 71*91f16700Schasinglulu uint32_t i; 72*91f16700Schasinglulu 73*91f16700Schasinglulu for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) { 74*91f16700Schasinglulu io_write_64(QOSBW_FIX_QOS_BANK0 + i * 8, mstat_fix[i]); 75*91f16700Schasinglulu io_write_64(QOSBW_FIX_QOS_BANK1 + i * 8, mstat_fix[i]); 76*91f16700Schasinglulu } 77*91f16700Schasinglulu for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) { 78*91f16700Schasinglulu io_write_64(QOSBW_BE_QOS_BANK0 + i * 8, mstat_be[i]); 79*91f16700Schasinglulu io_write_64(QOSBW_BE_QOS_BANK1 + i * 8, mstat_be[i]); 80*91f16700Schasinglulu } 81*91f16700Schasinglulu 82*91f16700Schasinglulu /* 3DG bus Leaf setting */ 83*91f16700Schasinglulu io_write_32(0xFD820808U, 0x00001234U); 84*91f16700Schasinglulu io_write_32(0xFD820800U, 0x0000003FU); 85*91f16700Schasinglulu io_write_32(0xFD821800U, 0x0000003FU); 86*91f16700Schasinglulu io_write_32(0xFD822800U, 0x0000003FU); 87*91f16700Schasinglulu io_write_32(0xFD823800U, 0x0000003FU); 88*91f16700Schasinglulu io_write_32(0xFD824800U, 0x0000003FU); 89*91f16700Schasinglulu io_write_32(0xFD825800U, 0x0000003FU); 90*91f16700Schasinglulu io_write_32(0xFD826800U, 0x0000003FU); 91*91f16700Schasinglulu io_write_32(0xFD827800U, 0x0000003FU); 92*91f16700Schasinglulu 93*91f16700Schasinglulu /* Resource Alloc start */ 94*91f16700Schasinglulu io_write_32(QOSCTRL_RAEN, 0x00000001U); 95*91f16700Schasinglulu 96*91f16700Schasinglulu /* QOSBW start */ 97*91f16700Schasinglulu io_write_32(QOSCTRL_STATQC, 0x00000001U); 98*91f16700Schasinglulu #else 99*91f16700Schasinglulu NOTICE("BL2: QoS is None\n"); 100*91f16700Schasinglulu 101*91f16700Schasinglulu /* Resource Alloc setting */ 102*91f16700Schasinglulu io_write_32(QOSCTRL_EC, 0x00080001U); /* need for H3 v1.* */ 103*91f16700Schasinglulu #endif /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */ 104*91f16700Schasinglulu } 105