1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #include <stdint.h> 8*91f16700Schasinglulu #include <string.h> 9*91f16700Schasinglulu 10*91f16700Schasinglulu #include <common/debug.h> 11*91f16700Schasinglulu #include <lib/mmio.h> 12*91f16700Schasinglulu 13*91f16700Schasinglulu #include "cpg_registers.h" 14*91f16700Schasinglulu #include "rcar_def.h" 15*91f16700Schasinglulu #include "rcar_private.h" 16*91f16700Schasinglulu #include "rpc_registers.h" 17*91f16700Schasinglulu 18*91f16700Schasinglulu #define MSTPSR9_RPC_BIT (0x00020000U) 19*91f16700Schasinglulu #define RPC_CMNCR_MD_BIT (0x80000000U) 20*91f16700Schasinglulu #define RPC_PHYCNT_CAL BIT(31) 21*91f16700Schasinglulu #define RPC_PHYCNT_STRTIM_M3V1 (0x6 << 15UL) 22*91f16700Schasinglulu #define RPC_PHYCNT_STRTIM (0x7 << 15UL) 23*91f16700Schasinglulu 24*91f16700Schasinglulu static void rpc_enable(void) 25*91f16700Schasinglulu { 26*91f16700Schasinglulu /* Enable clock supply to RPC. */ 27*91f16700Schasinglulu mstpcr_write(CPG_SMSTPCR9, CPG_MSTPSR9, MSTPSR9_RPC_BIT); 28*91f16700Schasinglulu } 29*91f16700Schasinglulu 30*91f16700Schasinglulu static void rpc_setup(void) 31*91f16700Schasinglulu { 32*91f16700Schasinglulu uint32_t product, cut, reg, phy_strtim; 33*91f16700Schasinglulu 34*91f16700Schasinglulu if (mmio_read_32(RPC_CMNCR) & RPC_CMNCR_MD_BIT) 35*91f16700Schasinglulu mmio_clrbits_32(RPC_CMNCR, RPC_CMNCR_MD_BIT); 36*91f16700Schasinglulu 37*91f16700Schasinglulu product = mmio_read_32(RCAR_PRR) & PRR_PRODUCT_MASK; 38*91f16700Schasinglulu cut = mmio_read_32(RCAR_PRR) & PRR_CUT_MASK; 39*91f16700Schasinglulu 40*91f16700Schasinglulu if ((product == PRR_PRODUCT_M3) && (cut < PRR_PRODUCT_30)) 41*91f16700Schasinglulu phy_strtim = RPC_PHYCNT_STRTIM_M3V1; 42*91f16700Schasinglulu else 43*91f16700Schasinglulu phy_strtim = RPC_PHYCNT_STRTIM; 44*91f16700Schasinglulu 45*91f16700Schasinglulu reg = mmio_read_32(RPC_PHYCNT); 46*91f16700Schasinglulu reg &= ~RPC_PHYCNT_STRTIM; 47*91f16700Schasinglulu reg |= phy_strtim; 48*91f16700Schasinglulu mmio_write_32(RPC_PHYCNT, reg); 49*91f16700Schasinglulu reg |= RPC_PHYCNT_CAL; 50*91f16700Schasinglulu mmio_write_32(RPC_PHYCNT, reg); 51*91f16700Schasinglulu } 52*91f16700Schasinglulu 53*91f16700Schasinglulu void rcar_rpc_init(void) 54*91f16700Schasinglulu { 55*91f16700Schasinglulu rpc_enable(); 56*91f16700Schasinglulu rpc_setup(); 57*91f16700Schasinglulu } 58