1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef PWRC_H 8*91f16700Schasinglulu #define PWRC_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #define PPOFFR_OFF 0x0 11*91f16700Schasinglulu #define PPONR_OFF 0x4 12*91f16700Schasinglulu #define PCOFFR_OFF 0x8 13*91f16700Schasinglulu #define PWKUPR_OFF 0xc 14*91f16700Schasinglulu #define PSYSR_OFF 0x10 15*91f16700Schasinglulu 16*91f16700Schasinglulu #define PWKUPR_WEN (1ull << 31) 17*91f16700Schasinglulu 18*91f16700Schasinglulu #define PSYSR_AFF_L2 (1U << 31) 19*91f16700Schasinglulu #define PSYSR_AFF_L1 (1 << 30) 20*91f16700Schasinglulu #define PSYSR_AFF_L0 (1 << 29) 21*91f16700Schasinglulu #define PSYSR_WEN (1 << 28) 22*91f16700Schasinglulu #define PSYSR_PC (1 << 27) 23*91f16700Schasinglulu #define PSYSR_PP (1 << 26) 24*91f16700Schasinglulu 25*91f16700Schasinglulu #define PSYSR_WK_SHIFT (24) 26*91f16700Schasinglulu #define PSYSR_WK_MASK (0x3) 27*91f16700Schasinglulu #define PSYSR_WK(x) (((x) >> PSYSR_WK_SHIFT) & PSYSR_WK_MASK) 28*91f16700Schasinglulu 29*91f16700Schasinglulu #define WKUP_COLD 0x0 30*91f16700Schasinglulu #define WKUP_RESET 0x1 31*91f16700Schasinglulu #define WKUP_PPONR 0x2 32*91f16700Schasinglulu #define WKUP_GICREQ 0x3 33*91f16700Schasinglulu 34*91f16700Schasinglulu #define RCAR_INVALID (0xffffffffU) 35*91f16700Schasinglulu #define PSYSR_INVALID 0xffffffff 36*91f16700Schasinglulu 37*91f16700Schasinglulu #define RCAR_CLUSTER_A53A57 (0U) 38*91f16700Schasinglulu #define RCAR_CLUSTER_CA53 (1U) 39*91f16700Schasinglulu #define RCAR_CLUSTER_CA57 (2U) 40*91f16700Schasinglulu 41*91f16700Schasinglulu extern u_register_t rcar_boot_mpidr; 42*91f16700Schasinglulu 43*91f16700Schasinglulu #ifndef __ASSEMBLER__ 44*91f16700Schasinglulu void rcar_pwrc_disable_interrupt_wakeup(u_register_t mpidr); 45*91f16700Schasinglulu void rcar_pwrc_enable_interrupt_wakeup(u_register_t mpidr); 46*91f16700Schasinglulu void rcar_pwrc_all_disable_interrupt_wakeup(void); 47*91f16700Schasinglulu void rcar_pwrc_clusteroff(u_register_t mpidr); 48*91f16700Schasinglulu void rcar_pwrc_cpuoff(u_register_t mpidr); 49*91f16700Schasinglulu void rcar_pwrc_cpuon(u_register_t mpidr); 50*91f16700Schasinglulu int32_t rcar_pwrc_cpu_on_check(u_register_t mpidr); 51*91f16700Schasinglulu void rcar_pwrc_setup(void); 52*91f16700Schasinglulu 53*91f16700Schasinglulu uint32_t rcar_pwrc_get_cpu_wkr(u_register_t mpidr); 54*91f16700Schasinglulu uint32_t rcar_pwrc_status(u_register_t mpidr); 55*91f16700Schasinglulu uint32_t rcar_pwrc_get_cluster(void); 56*91f16700Schasinglulu uint32_t rcar_pwrc_get_mpidr_cluster(u_register_t mpidr); 57*91f16700Schasinglulu uint32_t rcar_pwrc_get_cpu_num(uint32_t cluster_type); 58*91f16700Schasinglulu void rcar_pwrc_restore_timer_state(void); 59*91f16700Schasinglulu void plat_secondary_reset(void); 60*91f16700Schasinglulu 61*91f16700Schasinglulu void rcar_pwrc_code_copy_to_system_ram(void); 62*91f16700Schasinglulu 63*91f16700Schasinglulu #if !PMIC_ROHM_BD9571 64*91f16700Schasinglulu void rcar_pwrc_system_reset(void); 65*91f16700Schasinglulu #endif 66*91f16700Schasinglulu 67*91f16700Schasinglulu #if RCAR_SYSTEM_SUSPEND 68*91f16700Schasinglulu void rcar_pwrc_go_suspend_to_ram(void); 69*91f16700Schasinglulu void rcar_pwrc_set_suspend_to_ram(void); 70*91f16700Schasinglulu void rcar_pwrc_init_suspend_to_ram(void); 71*91f16700Schasinglulu void rcar_pwrc_suspend_to_ram(void); 72*91f16700Schasinglulu #endif 73*91f16700Schasinglulu 74*91f16700Schasinglulu extern uint32_t rcar_pwrc_switch_stack(uintptr_t jump, uintptr_t stack, 75*91f16700Schasinglulu void *arg); 76*91f16700Schasinglulu #endif 77*91f16700Schasinglulu 78*91f16700Schasinglulu #endif /* PWRC_H */ 79