1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright 2021 NXP 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu * 6*91f16700Schasinglulu */ 7*91f16700Schasinglulu 8*91f16700Schasinglulu #include <assert.h> 9*91f16700Schasinglulu 10*91f16700Schasinglulu #include <common/debug.h> 11*91f16700Schasinglulu #include <lib/mmio.h> 12*91f16700Schasinglulu #include <lib/xlat_tables/xlat_tables_v2.h> 13*91f16700Schasinglulu #include <qspi.h> 14*91f16700Schasinglulu 15*91f16700Schasinglulu int qspi_io_setup(uintptr_t nxp_qspi_flash_addr, 16*91f16700Schasinglulu size_t nxp_qspi_flash_size, 17*91f16700Schasinglulu uintptr_t fip_offset) 18*91f16700Schasinglulu { 19*91f16700Schasinglulu uint32_t qspi_mcr_val = qspi_in32(CHS_QSPI_MCR); 20*91f16700Schasinglulu 21*91f16700Schasinglulu /* Enable and change endianness of QSPI IP */ 22*91f16700Schasinglulu qspi_out32(CHS_QSPI_MCR, (qspi_mcr_val | CHS_QSPI_64LE)); 23*91f16700Schasinglulu 24*91f16700Schasinglulu /* Adding QSPI Memory Map in XLAT Table */ 25*91f16700Schasinglulu mmap_add_region(nxp_qspi_flash_addr, nxp_qspi_flash_addr, 26*91f16700Schasinglulu nxp_qspi_flash_size, MT_MEMORY | MT_RW); 27*91f16700Schasinglulu 28*91f16700Schasinglulu return 0; 29*91f16700Schasinglulu } 30