1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright 2021 NXP 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu * 6*91f16700Schasinglulu */ 7*91f16700Schasinglulu 8*91f16700Schasinglulu #include <arch.h> 9*91f16700Schasinglulu #include <arch_helpers.h> 10*91f16700Schasinglulu #include <common/debug.h> 11*91f16700Schasinglulu #include <dcfg.h> 12*91f16700Schasinglulu #include <lib/mmio.h> 13*91f16700Schasinglulu #include <pmu.h> 14*91f16700Schasinglulu 15*91f16700Schasinglulu void enable_timer_base_to_cluster(uintptr_t nxp_pmu_addr) 16*91f16700Schasinglulu { 17*91f16700Schasinglulu uint32_t *cltbenr = NULL; 18*91f16700Schasinglulu uint32_t cltbenr_val = 0U; 19*91f16700Schasinglulu 20*91f16700Schasinglulu cltbenr = (uint32_t *)(nxp_pmu_addr 21*91f16700Schasinglulu + CLUST_TIMER_BASE_ENBL_OFFSET); 22*91f16700Schasinglulu 23*91f16700Schasinglulu cltbenr_val = mmio_read_32((uintptr_t)cltbenr); 24*91f16700Schasinglulu 25*91f16700Schasinglulu cltbenr_val = cltbenr_val 26*91f16700Schasinglulu | (1 << MPIDR_AFFLVL1_VAL(read_mpidr_el1())); 27*91f16700Schasinglulu 28*91f16700Schasinglulu mmio_write_32((uintptr_t)cltbenr, cltbenr_val); 29*91f16700Schasinglulu 30*91f16700Schasinglulu VERBOSE("Enable cluster time base\n"); 31*91f16700Schasinglulu } 32*91f16700Schasinglulu 33*91f16700Schasinglulu /* 34*91f16700Schasinglulu * Enable core timebase. In certain Layerscape SoCs, the clock for each core's 35*91f16700Schasinglulu * has an enable bit in the PMU Physical Core Time Base Enable 36*91f16700Schasinglulu * Register (PCTBENR), which allows the watchdog to operate. 37*91f16700Schasinglulu */ 38*91f16700Schasinglulu 39*91f16700Schasinglulu void enable_core_tb(uintptr_t nxp_pmu_addr) 40*91f16700Schasinglulu { 41*91f16700Schasinglulu uint32_t *pctbenr = (uint32_t *) (nxp_pmu_addr + 42*91f16700Schasinglulu CORE_TIMEBASE_ENBL_OFFSET); 43*91f16700Schasinglulu 44*91f16700Schasinglulu mmio_write_32((uintptr_t)pctbenr, 0xff); 45*91f16700Schasinglulu } 46