1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright 2021 NXP 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu * 6*91f16700Schasinglulu */ 7*91f16700Schasinglulu 8*91f16700Schasinglulu #include <gicv2.h> 9*91f16700Schasinglulu #include <plat_gic.h> 10*91f16700Schasinglulu 11*91f16700Schasinglulu 12*91f16700Schasinglulu /* 13*91f16700Schasinglulu * NXP common helper to initialize the GICv3 only driver. 14*91f16700Schasinglulu */ 15*91f16700Schasinglulu void plat_ls_gic_driver_init(uintptr_t nxp_gicd_addr, 16*91f16700Schasinglulu uintptr_t nxp_gicc_addr, 17*91f16700Schasinglulu uint8_t plat_core_count, 18*91f16700Schasinglulu interrupt_prop_t *ls_interrupt_props, 19*91f16700Schasinglulu uint8_t ls_interrupt_prop_count, 20*91f16700Schasinglulu uint32_t *target_mask_array) 21*91f16700Schasinglulu { 22*91f16700Schasinglulu static struct gicv2_driver_data ls_gic_data; 23*91f16700Schasinglulu 24*91f16700Schasinglulu ls_gic_data.gicd_base = nxp_gicd_addr; 25*91f16700Schasinglulu ls_gic_data.gicc_base = nxp_gicc_addr; 26*91f16700Schasinglulu ls_gic_data.target_masks = target_mask_array; 27*91f16700Schasinglulu ls_gic_data.target_masks_num = plat_core_count; 28*91f16700Schasinglulu ls_gic_data.interrupt_props = ls_interrupt_props; 29*91f16700Schasinglulu ls_gic_data.interrupt_props_num = ls_interrupt_prop_count; 30*91f16700Schasinglulu 31*91f16700Schasinglulu gicv2_driver_init(&ls_gic_data); 32*91f16700Schasinglulu } 33*91f16700Schasinglulu 34*91f16700Schasinglulu void plat_ls_gic_init(void) 35*91f16700Schasinglulu { 36*91f16700Schasinglulu gicv2_distif_init(); 37*91f16700Schasinglulu gicv2_pcpu_distif_init(); 38*91f16700Schasinglulu gicv2_cpuif_enable(); 39*91f16700Schasinglulu } 40*91f16700Schasinglulu 41*91f16700Schasinglulu /****************************************************************************** 42*91f16700Schasinglulu * ARM common helper to enable the GICv2 CPU interface 43*91f16700Schasinglulu *****************************************************************************/ 44*91f16700Schasinglulu void plat_ls_gic_cpuif_enable(void) 45*91f16700Schasinglulu { 46*91f16700Schasinglulu gicv2_cpuif_enable(); 47*91f16700Schasinglulu } 48*91f16700Schasinglulu 49*91f16700Schasinglulu /****************************************************************************** 50*91f16700Schasinglulu * ARM common helper to disable the GICv2 CPU interface 51*91f16700Schasinglulu *****************************************************************************/ 52*91f16700Schasinglulu void plat_ls_gic_cpuif_disable(void) 53*91f16700Schasinglulu { 54*91f16700Schasinglulu gicv2_cpuif_disable(); 55*91f16700Schasinglulu } 56*91f16700Schasinglulu 57*91f16700Schasinglulu /****************************************************************************** 58*91f16700Schasinglulu * NXP common helper to initialize GICv2 per cpu 59*91f16700Schasinglulu *****************************************************************************/ 60*91f16700Schasinglulu void plat_gic_pcpu_init(void) 61*91f16700Schasinglulu { 62*91f16700Schasinglulu gicv2_pcpu_distif_init(); 63*91f16700Schasinglulu gicv2_cpuif_enable(); 64*91f16700Schasinglulu } 65*91f16700Schasinglulu 66*91f16700Schasinglulu /****************************************************************************** 67*91f16700Schasinglulu * Stubs for Redistributor power management. Although GICv2 doesn't have 68*91f16700Schasinglulu * Redistributor interface, these are provided for the sake of uniform GIC API 69*91f16700Schasinglulu *****************************************************************************/ 70*91f16700Schasinglulu void plat_ls_gic_redistif_on(void) 71*91f16700Schasinglulu { 72*91f16700Schasinglulu } 73*91f16700Schasinglulu 74*91f16700Schasinglulu void plat_ls_gic_redistif_off(void) 75*91f16700Schasinglulu { 76*91f16700Schasinglulu } 77