1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright 2020 NXP 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu * 6*91f16700Schasinglulu */ 7*91f16700Schasinglulu 8*91f16700Schasinglulu #ifndef FLEXSPI_NOR_H 9*91f16700Schasinglulu #define FLEXSPI_NOR_H 10*91f16700Schasinglulu 11*91f16700Schasinglulu int flexspi_nor_io_setup(uintptr_t nxp_flexspi_flash_addr, 12*91f16700Schasinglulu size_t nxp_flexspi_flash_size, 13*91f16700Schasinglulu uint32_t fspi_base_reg_addr); 14*91f16700Schasinglulu 15*91f16700Schasinglulu #endif /* FLEXSPI_NOR_H */ 16