1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright 2021 NXP 3*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 4*91f16700Schasinglulu * 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef _INPUT_H_ 8*91f16700Schasinglulu #define _INPUT_H_ 9*91f16700Schasinglulu 10*91f16700Schasinglulu enum dram_types { 11*91f16700Schasinglulu DDR4, 12*91f16700Schasinglulu DDR3, 13*91f16700Schasinglulu LPDDR4, 14*91f16700Schasinglulu LPDDR3, 15*91f16700Schasinglulu LPDDR2, 16*91f16700Schasinglulu DDR5, 17*91f16700Schasinglulu }; 18*91f16700Schasinglulu 19*91f16700Schasinglulu enum dimm_types { 20*91f16700Schasinglulu UDIMM, 21*91f16700Schasinglulu SODIMM, 22*91f16700Schasinglulu RDIMM, 23*91f16700Schasinglulu LRDIMM, 24*91f16700Schasinglulu NODIMM, 25*91f16700Schasinglulu }; 26*91f16700Schasinglulu 27*91f16700Schasinglulu struct input_basic { 28*91f16700Schasinglulu enum dram_types dram_type; 29*91f16700Schasinglulu enum dimm_types dimm_type; 30*91f16700Schasinglulu int lp4x_mode; /* 0x1 = lpddr4x mode, when dram_type is lpddr4 31*91f16700Schasinglulu */ 32*91f16700Schasinglulu /* not used for protocols other than lpddr4 */ 33*91f16700Schasinglulu int num_dbyte; /* number of dbytes physically instantiated */ 34*91f16700Schasinglulu int num_active_dbyte_dfi0; /* number of active dbytes to be 35*91f16700Schasinglulu * controlled by dfi0 36*91f16700Schasinglulu */ 37*91f16700Schasinglulu int num_active_dbyte_dfi1; /* number of active dbytes to be 38*91f16700Schasinglulu * controlled by dfi1. Not used for 39*91f16700Schasinglulu * protocols other than lpddr3 and 40*91f16700Schasinglulu * lpddr4 41*91f16700Schasinglulu */ 42*91f16700Schasinglulu int num_anib; /* number of anibs physically instantiated */ 43*91f16700Schasinglulu int num_rank_dfi0; /* number of ranks in dfi0 channel */ 44*91f16700Schasinglulu int num_rank_dfi1; /* number of ranks in dfi1 channel */ 45*91f16700Schasinglulu int dram_data_width; /* 4,8,16 or 32 depending on protocol and dram 46*91f16700Schasinglulu * type 47*91f16700Schasinglulu */ 48*91f16700Schasinglulu int num_pstates; 49*91f16700Schasinglulu int frequency; /* memclk frequency in mhz -- round up */ 50*91f16700Schasinglulu int pll_bypass; /* pll bypass enable */ 51*91f16700Schasinglulu int dfi_freq_ratio; /* selected dfi frequency ratio */ 52*91f16700Schasinglulu int dfi1exists; /* whether they phy config has dfi1 channel */ 53*91f16700Schasinglulu int train2d; 54*91f16700Schasinglulu int hard_macro_ver; 55*91f16700Schasinglulu int read_dbienable; 56*91f16700Schasinglulu int dfi_mode; /* no longer used */ 57*91f16700Schasinglulu }; 58*91f16700Schasinglulu 59*91f16700Schasinglulu struct input_advanced { 60*91f16700Schasinglulu int d4rx_preamble_length; 61*91f16700Schasinglulu int d4tx_preamble_length; 62*91f16700Schasinglulu int ext_cal_res_val; /* external pull-down resistor */ 63*91f16700Schasinglulu int is2ttiming; 64*91f16700Schasinglulu int odtimpedance; 65*91f16700Schasinglulu int tx_impedance; 66*91f16700Schasinglulu int atx_impedance; 67*91f16700Schasinglulu int mem_alert_en; 68*91f16700Schasinglulu int mem_alert_puimp; 69*91f16700Schasinglulu int mem_alert_vref_level; 70*91f16700Schasinglulu int mem_alert_sync_bypass; 71*91f16700Schasinglulu int dis_dyn_adr_tri; 72*91f16700Schasinglulu int phy_mstr_train_interval; 73*91f16700Schasinglulu int phy_mstr_max_req_to_ack; 74*91f16700Schasinglulu int wdqsext; 75*91f16700Schasinglulu int cal_interval; 76*91f16700Schasinglulu int cal_once; 77*91f16700Schasinglulu int dram_byte_swap; 78*91f16700Schasinglulu int rx_en_back_off; 79*91f16700Schasinglulu int train_sequence_ctrl; 80*91f16700Schasinglulu int phy_gen2_umctl_opt; 81*91f16700Schasinglulu int phy_gen2_umctl_f0rc5x; 82*91f16700Schasinglulu int tx_slew_rise_dq; 83*91f16700Schasinglulu int tx_slew_fall_dq; 84*91f16700Schasinglulu int tx_slew_rise_ac; 85*91f16700Schasinglulu int tx_slew_fall_ac; 86*91f16700Schasinglulu int enable_high_clk_skew_fix; 87*91f16700Schasinglulu int disable_unused_addr_lns; 88*91f16700Schasinglulu int phy_init_sequence_num; 89*91f16700Schasinglulu int cs_mode; /* rdimm */ 90*91f16700Schasinglulu int cast_cs_to_cid; /* rdimm */ 91*91f16700Schasinglulu }; 92*91f16700Schasinglulu 93*91f16700Schasinglulu struct input { 94*91f16700Schasinglulu struct input_basic basic; 95*91f16700Schasinglulu struct input_advanced adv; 96*91f16700Schasinglulu unsigned int mr[7]; 97*91f16700Schasinglulu unsigned int cs_d0; 98*91f16700Schasinglulu unsigned int cs_d1; 99*91f16700Schasinglulu unsigned int mirror; 100*91f16700Schasinglulu unsigned int odt[4]; 101*91f16700Schasinglulu unsigned int rcw[16]; 102*91f16700Schasinglulu unsigned int rcw3x; 103*91f16700Schasinglulu unsigned int vref; 104*91f16700Schasinglulu }; 105*91f16700Schasinglulu 106*91f16700Schasinglulu #endif 107