1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (C) 2016 - 2018 Marvell International Ltd. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu * https://spdx.org/licenses 6*91f16700Schasinglulu */ 7*91f16700Schasinglulu 8*91f16700Schasinglulu /* IOW unit device driver for Marvell CP110 and CP115 SoCs */ 9*91f16700Schasinglulu 10*91f16700Schasinglulu #include <inttypes.h> 11*91f16700Schasinglulu #include <stdint.h> 12*91f16700Schasinglulu 13*91f16700Schasinglulu #include <arch_helpers.h> 14*91f16700Schasinglulu #include <common/debug.h> 15*91f16700Schasinglulu #include <drivers/marvell/iob.h> 16*91f16700Schasinglulu #include <lib/mmio.h> 17*91f16700Schasinglulu 18*91f16700Schasinglulu #include <armada_common.h> 19*91f16700Schasinglulu #include <mvebu.h> 20*91f16700Schasinglulu #include <mvebu_def.h> 21*91f16700Schasinglulu 22*91f16700Schasinglulu #if LOG_LEVEL >= LOG_LEVEL_INFO 23*91f16700Schasinglulu #define DEBUG_ADDR_MAP 24*91f16700Schasinglulu #endif 25*91f16700Schasinglulu 26*91f16700Schasinglulu #define MVEBU_IOB_OFFSET (0x190000) 27*91f16700Schasinglulu #define MVEBU_IOB_MAX_WINS 16 28*91f16700Schasinglulu 29*91f16700Schasinglulu /* common defines */ 30*91f16700Schasinglulu #define WIN_ENABLE_BIT (0x1) 31*91f16700Schasinglulu /* Physical address of the base of the window = {AddrLow[19:0],20`h0} */ 32*91f16700Schasinglulu #define ADDRESS_SHIFT (20 - 4) 33*91f16700Schasinglulu #define ADDRESS_MASK (0xFFFFFFF0) 34*91f16700Schasinglulu #define IOB_WIN_ALIGNMENT (0x100000) 35*91f16700Schasinglulu 36*91f16700Schasinglulu /* IOB registers */ 37*91f16700Schasinglulu #define IOB_WIN_CR_OFFSET(win) (iob_base + 0x0 + (0x20 * win)) 38*91f16700Schasinglulu #define IOB_TARGET_ID_OFFSET (8) 39*91f16700Schasinglulu #define IOB_TARGET_ID_MASK (0xF) 40*91f16700Schasinglulu 41*91f16700Schasinglulu #define IOB_WIN_SCR_OFFSET(win) (iob_base + 0x4 + (0x20 * win)) 42*91f16700Schasinglulu #define IOB_WIN_ENA_CTRL_WRITE_SECURE (0x1) 43*91f16700Schasinglulu #define IOB_WIN_ENA_CTRL_READ_SECURE (0x2) 44*91f16700Schasinglulu #define IOB_WIN_ENA_WRITE_SECURE (0x4) 45*91f16700Schasinglulu #define IOB_WIN_ENA_READ_SECURE (0x8) 46*91f16700Schasinglulu 47*91f16700Schasinglulu #define IOB_WIN_ALR_OFFSET(win) (iob_base + 0x8 + (0x20 * win)) 48*91f16700Schasinglulu #define IOB_WIN_AHR_OFFSET(win) (iob_base + 0xC + (0x20 * win)) 49*91f16700Schasinglulu 50*91f16700Schasinglulu #define IOB_WIN_DIOB_CR_OFFSET(win) (iob_base + 0x10 + (0x20 * win)) 51*91f16700Schasinglulu #define IOB_WIN_XOR0_DIOB_EN BIT(0) 52*91f16700Schasinglulu #define IOB_WIN_XOR1_DIOB_EN BIT(1) 53*91f16700Schasinglulu 54*91f16700Schasinglulu uintptr_t iob_base; 55*91f16700Schasinglulu 56*91f16700Schasinglulu static void iob_win_check(struct addr_map_win *win, uint32_t win_num) 57*91f16700Schasinglulu { 58*91f16700Schasinglulu /* check if address is aligned to the size */ 59*91f16700Schasinglulu if (IS_NOT_ALIGN(win->base_addr, IOB_WIN_ALIGNMENT)) { 60*91f16700Schasinglulu win->base_addr = ALIGN_UP(win->base_addr, IOB_WIN_ALIGNMENT); 61*91f16700Schasinglulu ERROR("Window %d: base address unaligned to 0x%x\n", 62*91f16700Schasinglulu win_num, IOB_WIN_ALIGNMENT); 63*91f16700Schasinglulu printf("Align up the base address to 0x%" PRIx64 "\n", 64*91f16700Schasinglulu win->base_addr); 65*91f16700Schasinglulu } 66*91f16700Schasinglulu 67*91f16700Schasinglulu /* size parameter validity check */ 68*91f16700Schasinglulu if (IS_NOT_ALIGN(win->win_size, IOB_WIN_ALIGNMENT)) { 69*91f16700Schasinglulu win->win_size = ALIGN_UP(win->win_size, IOB_WIN_ALIGNMENT); 70*91f16700Schasinglulu ERROR("Window %d: window size unaligned to 0x%x\n", win_num, 71*91f16700Schasinglulu IOB_WIN_ALIGNMENT); 72*91f16700Schasinglulu printf("Aligning size to 0x%" PRIx64 "\n", win->win_size); 73*91f16700Schasinglulu } 74*91f16700Schasinglulu } 75*91f16700Schasinglulu 76*91f16700Schasinglulu static void iob_enable_win(struct addr_map_win *win, uint32_t win_id) 77*91f16700Schasinglulu { 78*91f16700Schasinglulu uint32_t iob_win_reg; 79*91f16700Schasinglulu uint32_t alr, ahr; 80*91f16700Schasinglulu uint64_t end_addr; 81*91f16700Schasinglulu uint32_t reg_en; 82*91f16700Schasinglulu 83*91f16700Schasinglulu /* move XOR (DMA) to use WIN1 which is used for PCI-EP address space */ 84*91f16700Schasinglulu reg_en = IOB_WIN_XOR0_DIOB_EN | IOB_WIN_XOR1_DIOB_EN; 85*91f16700Schasinglulu iob_win_reg = mmio_read_32(IOB_WIN_DIOB_CR_OFFSET(0)); 86*91f16700Schasinglulu iob_win_reg &= ~reg_en; 87*91f16700Schasinglulu mmio_write_32(IOB_WIN_DIOB_CR_OFFSET(0), iob_win_reg); 88*91f16700Schasinglulu 89*91f16700Schasinglulu iob_win_reg = mmio_read_32(IOB_WIN_DIOB_CR_OFFSET(1)); 90*91f16700Schasinglulu iob_win_reg |= reg_en; 91*91f16700Schasinglulu mmio_write_32(IOB_WIN_DIOB_CR_OFFSET(1), iob_win_reg); 92*91f16700Schasinglulu 93*91f16700Schasinglulu end_addr = (win->base_addr + win->win_size - 1); 94*91f16700Schasinglulu alr = (uint32_t)((win->base_addr >> ADDRESS_SHIFT) & ADDRESS_MASK); 95*91f16700Schasinglulu ahr = (uint32_t)((end_addr >> ADDRESS_SHIFT) & ADDRESS_MASK); 96*91f16700Schasinglulu 97*91f16700Schasinglulu mmio_write_32(IOB_WIN_ALR_OFFSET(win_id), alr); 98*91f16700Schasinglulu mmio_write_32(IOB_WIN_AHR_OFFSET(win_id), ahr); 99*91f16700Schasinglulu 100*91f16700Schasinglulu iob_win_reg = WIN_ENABLE_BIT; 101*91f16700Schasinglulu iob_win_reg |= (win->target_id & IOB_TARGET_ID_MASK) 102*91f16700Schasinglulu << IOB_TARGET_ID_OFFSET; 103*91f16700Schasinglulu mmio_write_32(IOB_WIN_CR_OFFSET(win_id), iob_win_reg); 104*91f16700Schasinglulu 105*91f16700Schasinglulu } 106*91f16700Schasinglulu 107*91f16700Schasinglulu #ifdef DEBUG_ADDR_MAP 108*91f16700Schasinglulu static void dump_iob(void) 109*91f16700Schasinglulu { 110*91f16700Schasinglulu uint32_t win_id, win_cr, alr, ahr; 111*91f16700Schasinglulu uint8_t target_id; 112*91f16700Schasinglulu uint64_t start, end; 113*91f16700Schasinglulu char *iob_target_name[IOB_MAX_TID] = { 114*91f16700Schasinglulu "CFG ", "MCI0 ", "PEX1 ", "PEX2 ", 115*91f16700Schasinglulu "PEX0 ", "NAND ", "RUNIT", "MCI1 " }; 116*91f16700Schasinglulu 117*91f16700Schasinglulu /* Dump all IOB windows */ 118*91f16700Schasinglulu printf("bank id target start end\n"); 119*91f16700Schasinglulu printf("----------------------------------------------------\n"); 120*91f16700Schasinglulu for (win_id = 0; win_id < MVEBU_IOB_MAX_WINS; win_id++) { 121*91f16700Schasinglulu win_cr = mmio_read_32(IOB_WIN_CR_OFFSET(win_id)); 122*91f16700Schasinglulu if (win_cr & WIN_ENABLE_BIT) { 123*91f16700Schasinglulu target_id = (win_cr >> IOB_TARGET_ID_OFFSET) & 124*91f16700Schasinglulu IOB_TARGET_ID_MASK; 125*91f16700Schasinglulu alr = mmio_read_32(IOB_WIN_ALR_OFFSET(win_id)); 126*91f16700Schasinglulu start = ((uint64_t)alr << ADDRESS_SHIFT); 127*91f16700Schasinglulu if (win_id != 0) { 128*91f16700Schasinglulu ahr = mmio_read_32(IOB_WIN_AHR_OFFSET(win_id)); 129*91f16700Schasinglulu end = (((uint64_t)ahr + 0x10) << ADDRESS_SHIFT); 130*91f16700Schasinglulu } else { 131*91f16700Schasinglulu /* Window #0 size is hardcoded to 16MB, as it's 132*91f16700Schasinglulu * reserved for CP configuration space. 133*91f16700Schasinglulu */ 134*91f16700Schasinglulu end = start + (16 << 20); 135*91f16700Schasinglulu } 136*91f16700Schasinglulu printf("iob %02d %s 0x%016" PRIx64 " 0x%016" PRIx64 "\n", 137*91f16700Schasinglulu win_id, iob_target_name[target_id], 138*91f16700Schasinglulu start, end); 139*91f16700Schasinglulu } 140*91f16700Schasinglulu } 141*91f16700Schasinglulu } 142*91f16700Schasinglulu #endif 143*91f16700Schasinglulu 144*91f16700Schasinglulu void iob_cfg_space_update(int ap_idx, int cp_idx, uintptr_t base, 145*91f16700Schasinglulu uintptr_t new_base) 146*91f16700Schasinglulu { 147*91f16700Schasinglulu debug_enter(); 148*91f16700Schasinglulu 149*91f16700Schasinglulu iob_base = base + MVEBU_IOB_OFFSET; 150*91f16700Schasinglulu 151*91f16700Schasinglulu NOTICE("Change the base address of AP%d-CP%d to %lx\n", 152*91f16700Schasinglulu ap_idx, cp_idx, new_base); 153*91f16700Schasinglulu mmio_write_32(IOB_WIN_ALR_OFFSET(0), new_base >> ADDRESS_SHIFT); 154*91f16700Schasinglulu 155*91f16700Schasinglulu iob_base = new_base + MVEBU_IOB_OFFSET; 156*91f16700Schasinglulu 157*91f16700Schasinglulu /* Make sure the address was configured by the CPU before 158*91f16700Schasinglulu * any possible access to the CP. 159*91f16700Schasinglulu */ 160*91f16700Schasinglulu dsb(); 161*91f16700Schasinglulu 162*91f16700Schasinglulu debug_exit(); 163*91f16700Schasinglulu } 164*91f16700Schasinglulu 165*91f16700Schasinglulu int init_iob(uintptr_t base) 166*91f16700Schasinglulu { 167*91f16700Schasinglulu struct addr_map_win *win; 168*91f16700Schasinglulu uint32_t win_id, win_reg; 169*91f16700Schasinglulu uint32_t win_count; 170*91f16700Schasinglulu 171*91f16700Schasinglulu INFO("Initializing IOB Address decoding\n"); 172*91f16700Schasinglulu 173*91f16700Schasinglulu /* Get the base address of the address decoding MBUS */ 174*91f16700Schasinglulu iob_base = base + MVEBU_IOB_OFFSET; 175*91f16700Schasinglulu 176*91f16700Schasinglulu /* Get the array of the windows and fill the map data */ 177*91f16700Schasinglulu marvell_get_iob_memory_map(&win, &win_count, base); 178*91f16700Schasinglulu if (win_count <= 0) { 179*91f16700Schasinglulu INFO("no windows configurations found\n"); 180*91f16700Schasinglulu return 0; 181*91f16700Schasinglulu } else if (win_count > (MVEBU_IOB_MAX_WINS - 1)) { 182*91f16700Schasinglulu ERROR("IOB mem map array > than max available windows (%d)\n", 183*91f16700Schasinglulu MVEBU_IOB_MAX_WINS); 184*91f16700Schasinglulu win_count = MVEBU_IOB_MAX_WINS; 185*91f16700Schasinglulu } 186*91f16700Schasinglulu 187*91f16700Schasinglulu /* disable all IOB windows, start from win_id = 1 188*91f16700Schasinglulu * because can't disable internal register window 189*91f16700Schasinglulu */ 190*91f16700Schasinglulu for (win_id = 1; win_id < MVEBU_IOB_MAX_WINS; win_id++) { 191*91f16700Schasinglulu win_reg = mmio_read_32(IOB_WIN_CR_OFFSET(win_id)); 192*91f16700Schasinglulu win_reg &= ~WIN_ENABLE_BIT; 193*91f16700Schasinglulu mmio_write_32(IOB_WIN_CR_OFFSET(win_id), win_reg); 194*91f16700Schasinglulu 195*91f16700Schasinglulu win_reg = ~IOB_WIN_ENA_CTRL_WRITE_SECURE; 196*91f16700Schasinglulu win_reg &= ~IOB_WIN_ENA_CTRL_READ_SECURE; 197*91f16700Schasinglulu win_reg &= ~IOB_WIN_ENA_WRITE_SECURE; 198*91f16700Schasinglulu win_reg &= ~IOB_WIN_ENA_READ_SECURE; 199*91f16700Schasinglulu mmio_write_32(IOB_WIN_SCR_OFFSET(win_id), win_reg); 200*91f16700Schasinglulu } 201*91f16700Schasinglulu 202*91f16700Schasinglulu for (win_id = 1; win_id < win_count + 1; win_id++, win++) { 203*91f16700Schasinglulu iob_win_check(win, win_id); 204*91f16700Schasinglulu iob_enable_win(win, win_id); 205*91f16700Schasinglulu } 206*91f16700Schasinglulu 207*91f16700Schasinglulu #ifdef DEBUG_ADDR_MAP 208*91f16700Schasinglulu dump_iob(); 209*91f16700Schasinglulu #endif 210*91f16700Schasinglulu 211*91f16700Schasinglulu INFO("Done IOB Address decoding Initializing\n"); 212*91f16700Schasinglulu 213*91f16700Schasinglulu return 0; 214*91f16700Schasinglulu } 215