1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (C) 2021 Marvell International Ltd. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu * https://spdx.org/licenses 6*91f16700Schasinglulu */ 7*91f16700Schasinglulu 8*91f16700Schasinglulu #include <plat_marvell.h> 9*91f16700Schasinglulu 10*91f16700Schasinglulu #define DEVICE_BASE 0xF0000000 11*91f16700Schasinglulu #define DDR_PHY_OFFSET 0x1000000 12*91f16700Schasinglulu #define DDR_PHY_BASE_ADDR (DEVICE_BASE + DDR_PHY_OFFSET) 13*91f16700Schasinglulu 14*91f16700Schasinglulu int mvebu_ddr_phy_write(uintptr_t offset, uint16_t data); 15*91f16700Schasinglulu int mvebu_ddr_phy_read(uintptr_t offset, uint16_t *read); 16