xref: /arm-trusted-firmware/drivers/marvell/ddr_phy_access.c (revision 91f16700b400a8c0651d24a598fc48ee2997a0d7)
1*91f16700Schasinglulu /*
2*91f16700Schasinglulu  * Copyright (C) 2021 Marvell International Ltd.
3*91f16700Schasinglulu  *
4*91f16700Schasinglulu  * SPDX-License-Identifier:     BSD-3-Clause
5*91f16700Schasinglulu  * https://spdx.org/licenses
6*91f16700Schasinglulu  */
7*91f16700Schasinglulu 
8*91f16700Schasinglulu #include "ddr_phy_access.h"
9*91f16700Schasinglulu #include <lib/mmio.h>
10*91f16700Schasinglulu #include <drivers/marvell/ccu.h>
11*91f16700Schasinglulu #include <errno.h>
12*91f16700Schasinglulu 
13*91f16700Schasinglulu #define DDR_PHY_END_ADDRESS	0x100000
14*91f16700Schasinglulu 
15*91f16700Schasinglulu #ifdef DDR_PHY_DEBUG
16*91f16700Schasinglulu #define debug_printf(...) printf(__VA_ARGS__)
17*91f16700Schasinglulu #else
18*91f16700Schasinglulu #define debug_printf(...)
19*91f16700Schasinglulu #endif
20*91f16700Schasinglulu 
21*91f16700Schasinglulu 
22*91f16700Schasinglulu /*
23*91f16700Schasinglulu  * This routine writes 'data' to specified 'address' offset,
24*91f16700Schasinglulu  * with optional debug print support
25*91f16700Schasinglulu  */
26*91f16700Schasinglulu int snps_fw_write(uintptr_t offset, uint16_t data)
27*91f16700Schasinglulu {
28*91f16700Schasinglulu 	debug_printf("In %s\n", __func__);
29*91f16700Schasinglulu 
30*91f16700Schasinglulu 	if (offset < DDR_PHY_END_ADDRESS) {
31*91f16700Schasinglulu 		mmio_write_16(DDR_PHY_BASE_ADDR + (2 * offset), data);
32*91f16700Schasinglulu 		return 0;
33*91f16700Schasinglulu 	}
34*91f16700Schasinglulu 	debug_printf("%s: illegal offset value: 0x%x\n", __func__, offset);
35*91f16700Schasinglulu 	return -EINVAL;
36*91f16700Schasinglulu }
37*91f16700Schasinglulu 
38*91f16700Schasinglulu int snps_fw_read(uintptr_t offset, uint16_t *read)
39*91f16700Schasinglulu {
40*91f16700Schasinglulu 	debug_printf("In %s\n", __func__);
41*91f16700Schasinglulu 
42*91f16700Schasinglulu 	if (offset < DDR_PHY_END_ADDRESS) {
43*91f16700Schasinglulu 		*read = mmio_read_16(DDR_PHY_BASE_ADDR + (2 * offset));
44*91f16700Schasinglulu 		return 0;
45*91f16700Schasinglulu 	}
46*91f16700Schasinglulu 	debug_printf("%s: illegal offset value: 0x%x\n", __func__, offset);
47*91f16700Schasinglulu 	return -EINVAL;
48*91f16700Schasinglulu }
49*91f16700Schasinglulu 
50*91f16700Schasinglulu int mvebu_ddr_phy_write(uintptr_t offset, uint16_t data)
51*91f16700Schasinglulu {
52*91f16700Schasinglulu 	return snps_fw_write(offset, data);
53*91f16700Schasinglulu }
54*91f16700Schasinglulu 
55*91f16700Schasinglulu int mvebu_ddr_phy_read(uintptr_t offset, uint16_t *read)
56*91f16700Schasinglulu {
57*91f16700Schasinglulu 	return snps_fw_read(offset, read);
58*91f16700Schasinglulu }
59