1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (C) 2018 Marvell International Ltd. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu * https://spdx.org/licenses 6*91f16700Schasinglulu */ 7*91f16700Schasinglulu 8*91f16700Schasinglulu #ifndef PHY_DEFAULT_PORTING_LAYER_H 9*91f16700Schasinglulu #define PHY_DEFAULT_PORTING_LAYER_H 10*91f16700Schasinglulu 11*91f16700Schasinglulu 12*91f16700Schasinglulu #define MAX_LANE_NR 6 13*91f16700Schasinglulu 14*91f16700Schasinglulu #warning "Using default comphy params - you may need to suit them to your board" 15*91f16700Schasinglulu 16*91f16700Schasinglulu static const struct xfi_params 17*91f16700Schasinglulu xfi_static_values_tab[AP_NUM][CP_NUM][MAX_LANE_NR] = { 18*91f16700Schasinglulu [0 ... AP_NUM-1][0 ... CP_NUM-1][0 ... MAX_LANE_NR-1] = { 19*91f16700Schasinglulu .g1_ffe_res_sel = 0x3, .g1_ffe_cap_sel = 0xf, .align90 = 0x5f, 20*91f16700Schasinglulu .g1_dfe_res = 0x2, .g1_amp = 0x1c, .g1_emph = 0xe, 21*91f16700Schasinglulu .g1_emph_en = 0x1, .g1_tx_amp_adj = 0x1, .g1_tx_emph_en = 0x1, 22*91f16700Schasinglulu .g1_tx_emph = 0x0, .g1_rx_selmuff = 0x1, .g1_rx_selmufi = 0x0, 23*91f16700Schasinglulu .g1_rx_selmupf = 0x2, .g1_rx_selmupi = 0x2, .valid = 1 24*91f16700Schasinglulu } 25*91f16700Schasinglulu }; 26*91f16700Schasinglulu 27*91f16700Schasinglulu static const struct sata_params 28*91f16700Schasinglulu sata_static_values_tab[AP_NUM][CP_NUM][MAX_LANE_NR] = { 29*91f16700Schasinglulu [0 ... AP_NUM-1][0 ... CP_NUM-1][0 ... MAX_LANE_NR-1] = { 30*91f16700Schasinglulu .g1_amp = 0x8, .g2_amp = 0xa, .g3_amp = 0x1e, 31*91f16700Schasinglulu .g1_emph = 0x1, .g2_emph = 0x2, .g3_emph = 0xe, 32*91f16700Schasinglulu .g1_emph_en = 0x1, .g2_emph_en = 0x1, .g3_emph_en = 0x1, 33*91f16700Schasinglulu .g1_tx_amp_adj = 0x1, .g2_tx_amp_adj = 0x1, 34*91f16700Schasinglulu .g3_tx_amp_adj = 0x1, 35*91f16700Schasinglulu .g1_tx_emph_en = 0x0, .g2_tx_emph_en = 0x0, 36*91f16700Schasinglulu .g3_tx_emph_en = 0x0, 37*91f16700Schasinglulu .g1_tx_emph = 0x1, .g2_tx_emph = 0x1, .g3_tx_emph = 0x1, 38*91f16700Schasinglulu .g3_dfe_res = 0x1, .g3_ffe_res_sel = 0x4, .g3_ffe_cap_sel = 0xf, 39*91f16700Schasinglulu .align90 = 0x61, 40*91f16700Schasinglulu .g1_rx_selmuff = 0x3, .g2_rx_selmuff = 0x3, 41*91f16700Schasinglulu .g3_rx_selmuff = 0x3, 42*91f16700Schasinglulu .g1_rx_selmufi = 0x0, .g2_rx_selmufi = 0x0, 43*91f16700Schasinglulu .g3_rx_selmufi = 0x3, 44*91f16700Schasinglulu .g1_rx_selmupf = 0x1, .g2_rx_selmupf = 0x1, 45*91f16700Schasinglulu .g3_rx_selmupf = 0x2, 46*91f16700Schasinglulu .g1_rx_selmupi = 0x0, .g2_rx_selmupi = 0x0, 47*91f16700Schasinglulu .g3_rx_selmupi = 0x2, 48*91f16700Schasinglulu .polarity_invert = COMPHY_POLARITY_NO_INVERT, 49*91f16700Schasinglulu .valid = 0x1 50*91f16700Schasinglulu }, 51*91f16700Schasinglulu }; 52*91f16700Schasinglulu 53*91f16700Schasinglulu static const struct usb_params 54*91f16700Schasinglulu usb_static_values_tab[AP_NUM][CP_NUM][MAX_LANE_NR] = { 55*91f16700Schasinglulu [0 ... AP_NUM-1][0 ... CP_NUM-1][0 ... MAX_LANE_NR-1] = { 56*91f16700Schasinglulu .polarity_invert = COMPHY_POLARITY_NO_INVERT 57*91f16700Schasinglulu }, 58*91f16700Schasinglulu }; 59*91f16700Schasinglulu #endif /* PHY_DEFAULT_PORTING_LAYER_H */ 60