1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (C) 2018 Marvell International Ltd. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu * https://spdx.org/licenses 6*91f16700Schasinglulu */ 7*91f16700Schasinglulu 8*91f16700Schasinglulu /* Those are parameters for xfi mode, which need to be tune for each board type. 9*91f16700Schasinglulu * For known DB boards the parameters was already calibrated and placed under 10*91f16700Schasinglulu * the plat/marvell/armada/a8k/<board_type>/board/phy-porting-layer.h 11*91f16700Schasinglulu */ 12*91f16700Schasinglulu struct xfi_params { 13*91f16700Schasinglulu uint8_t g1_ffe_res_sel; 14*91f16700Schasinglulu uint8_t g1_ffe_cap_sel; 15*91f16700Schasinglulu uint8_t align90; 16*91f16700Schasinglulu uint8_t g1_dfe_res; 17*91f16700Schasinglulu uint8_t g1_amp; 18*91f16700Schasinglulu uint8_t g1_emph; 19*91f16700Schasinglulu uint8_t g1_emph_en; 20*91f16700Schasinglulu uint8_t g1_tx_amp_adj; 21*91f16700Schasinglulu uint8_t g1_tx_emph_en; 22*91f16700Schasinglulu uint8_t g1_tx_emph; 23*91f16700Schasinglulu uint8_t g1_rx_selmuff; 24*91f16700Schasinglulu uint8_t g1_rx_selmufi; 25*91f16700Schasinglulu uint8_t g1_rx_selmupf; 26*91f16700Schasinglulu uint8_t g1_rx_selmupi; 27*91f16700Schasinglulu _Bool valid; 28*91f16700Schasinglulu }; 29*91f16700Schasinglulu 30*91f16700Schasinglulu struct sata_params { 31*91f16700Schasinglulu uint8_t g1_amp; 32*91f16700Schasinglulu uint8_t g2_amp; 33*91f16700Schasinglulu uint8_t g3_amp; 34*91f16700Schasinglulu 35*91f16700Schasinglulu uint8_t g1_emph; 36*91f16700Schasinglulu uint8_t g2_emph; 37*91f16700Schasinglulu uint8_t g3_emph; 38*91f16700Schasinglulu 39*91f16700Schasinglulu uint8_t g1_emph_en; 40*91f16700Schasinglulu uint8_t g2_emph_en; 41*91f16700Schasinglulu uint8_t g3_emph_en; 42*91f16700Schasinglulu 43*91f16700Schasinglulu uint8_t g1_tx_amp_adj; 44*91f16700Schasinglulu uint8_t g2_tx_amp_adj; 45*91f16700Schasinglulu uint8_t g3_tx_amp_adj; 46*91f16700Schasinglulu 47*91f16700Schasinglulu uint8_t g1_tx_emph_en; 48*91f16700Schasinglulu uint8_t g2_tx_emph_en; 49*91f16700Schasinglulu uint8_t g3_tx_emph_en; 50*91f16700Schasinglulu 51*91f16700Schasinglulu uint8_t g1_tx_emph; 52*91f16700Schasinglulu uint8_t g2_tx_emph; 53*91f16700Schasinglulu uint8_t g3_tx_emph; 54*91f16700Schasinglulu 55*91f16700Schasinglulu uint8_t g3_dfe_res; 56*91f16700Schasinglulu 57*91f16700Schasinglulu uint8_t g3_ffe_res_sel; 58*91f16700Schasinglulu 59*91f16700Schasinglulu uint8_t g3_ffe_cap_sel; 60*91f16700Schasinglulu 61*91f16700Schasinglulu uint8_t align90; 62*91f16700Schasinglulu 63*91f16700Schasinglulu uint8_t g1_rx_selmuff; 64*91f16700Schasinglulu uint8_t g2_rx_selmuff; 65*91f16700Schasinglulu uint8_t g3_rx_selmuff; 66*91f16700Schasinglulu 67*91f16700Schasinglulu uint8_t g1_rx_selmufi; 68*91f16700Schasinglulu uint8_t g2_rx_selmufi; 69*91f16700Schasinglulu uint8_t g3_rx_selmufi; 70*91f16700Schasinglulu 71*91f16700Schasinglulu uint8_t g1_rx_selmupf; 72*91f16700Schasinglulu uint8_t g2_rx_selmupf; 73*91f16700Schasinglulu uint8_t g3_rx_selmupf; 74*91f16700Schasinglulu 75*91f16700Schasinglulu uint8_t g1_rx_selmupi; 76*91f16700Schasinglulu uint8_t g2_rx_selmupi; 77*91f16700Schasinglulu uint8_t g3_rx_selmupi; 78*91f16700Schasinglulu 79*91f16700Schasinglulu uint8_t polarity_invert; 80*91f16700Schasinglulu 81*91f16700Schasinglulu _Bool valid; 82*91f16700Schasinglulu }; 83*91f16700Schasinglulu 84*91f16700Schasinglulu struct usb_params { 85*91f16700Schasinglulu uint8_t polarity_invert; 86*91f16700Schasinglulu }; 87*91f16700Schasinglulu 88*91f16700Schasinglulu int mvebu_cp110_comphy_is_pll_locked(uint64_t comphy_base, 89*91f16700Schasinglulu uint8_t comphy_index); 90*91f16700Schasinglulu int mvebu_cp110_comphy_power_off(uint64_t comphy_base, 91*91f16700Schasinglulu uint8_t comphy_index, uint64_t comphy_mode); 92*91f16700Schasinglulu int mvebu_cp110_comphy_power_on(uint64_t comphy_base, uint8_t comphy_index, 93*91f16700Schasinglulu uint64_t comphy_mode, 94*91f16700Schasinglulu uint64_t comphy_train_base); 95*91f16700Schasinglulu int mvebu_cp110_comphy_xfi_rx_training(uint64_t comphy_base, 96*91f16700Schasinglulu uint8_t comphy_index); 97*91f16700Schasinglulu int mvebu_cp110_comphy_digital_reset(uint64_t comphy_base, uint8_t comphy_index, 98*91f16700Schasinglulu uint32_t comphy_mode, uint32_t command); 99*91f16700Schasinglulu 100*91f16700Schasinglulu #define COMPHY_POLARITY_NO_INVERT 0 101*91f16700Schasinglulu #define COMPHY_POLARITY_TXD_INVERT 1 102*91f16700Schasinglulu #define COMPHY_POLARITY_RXD_INVERT 2 103