xref: /arm-trusted-firmware/drivers/imx/uart/imx_uart.h (revision 91f16700b400a8c0651d24a598fc48ee2997a0d7)
1*91f16700Schasinglulu /*
2*91f16700Schasinglulu  * Copyright (c) Linaro 2018 Limited and Contributors. All rights reserved.
3*91f16700Schasinglulu  *
4*91f16700Schasinglulu  * SPDX-License-Identifier: BSD-3-Clause
5*91f16700Schasinglulu  */
6*91f16700Schasinglulu #ifndef IMX_UART_H
7*91f16700Schasinglulu #define IMX_UART_H
8*91f16700Schasinglulu 
9*91f16700Schasinglulu #include <drivers/console.h>
10*91f16700Schasinglulu 
11*91f16700Schasinglulu #define IMX_UART_RXD_OFFSET	0x00
12*91f16700Schasinglulu #define IMX_UART_RXD_CHARRDY	BIT(15)
13*91f16700Schasinglulu #define IMX_UART_RXD_ERR	BIT(14)
14*91f16700Schasinglulu #define IMX_UART_RXD_OVERRUN	BIT(13)
15*91f16700Schasinglulu #define IMX_UART_RXD_FRMERR	BIT(12)
16*91f16700Schasinglulu #define IMX_UART_RXD_BRK	BIT(11)
17*91f16700Schasinglulu #define IMX_UART_RXD_PRERR	BIT(10)
18*91f16700Schasinglulu 
19*91f16700Schasinglulu #define IMX_UART_TXD_OFFSET	0x40
20*91f16700Schasinglulu 
21*91f16700Schasinglulu #define IMX_UART_CR1_OFFSET	0x80
22*91f16700Schasinglulu #define IMX_UART_CR1_ADEN	BIT(15)
23*91f16700Schasinglulu #define IMX_UART_CR1_ADBR	BIT(14)
24*91f16700Schasinglulu #define IMX_UART_CR1_TRDYEN	BIT(13)
25*91f16700Schasinglulu #define IMX_UART_CR1_IDEN	BIT(12)
26*91f16700Schasinglulu #define IMX_UART_CR1_RRDYEN	BIT(9)
27*91f16700Schasinglulu #define IMX_UART_CR1_RXDMAEN	BIT(8)
28*91f16700Schasinglulu #define IMX_UART_CR1_IREN	BIT(7)
29*91f16700Schasinglulu #define IMX_UART_CR1_TXMPTYEN	BIT(6)
30*91f16700Schasinglulu #define IMX_UART_CR1_RTSDEN	BIT(5)
31*91f16700Schasinglulu #define IMX_UART_CR1_SNDBRK	BIT(4)
32*91f16700Schasinglulu #define IMX_UART_CR1_TXDMAEN	BIT(3)
33*91f16700Schasinglulu #define IMX_UART_CR1_ATDMAEN	BIT(2)
34*91f16700Schasinglulu #define IMX_UART_CR1_DOZE	BIT(1)
35*91f16700Schasinglulu #define IMX_UART_CR1_UARTEN	BIT(0)
36*91f16700Schasinglulu 
37*91f16700Schasinglulu #define IMX_UART_CR2_OFFSET	0x84
38*91f16700Schasinglulu #define IMX_UART_CR2_ESCI	BIT(15)
39*91f16700Schasinglulu #define IMX_UART_CR2_IRTS	BIT(14)
40*91f16700Schasinglulu #define IMX_UART_CR2_CTSC	BIT(13)
41*91f16700Schasinglulu #define IMX_UART_CR2_CTS	BIT(12)
42*91f16700Schasinglulu #define IMX_UART_CR2_ESCEN	BIT(11)
43*91f16700Schasinglulu #define IMX_UART_CR2_PREN	BIT(8)
44*91f16700Schasinglulu #define IMX_UART_CR2_PROE	BIT(7)
45*91f16700Schasinglulu #define IMX_UART_CR2_STPB	BIT(6)
46*91f16700Schasinglulu #define IMX_UART_CR2_WS		BIT(5)
47*91f16700Schasinglulu #define IMX_UART_CR2_RTSEN	BIT(4)
48*91f16700Schasinglulu #define IMX_UART_CR2_ATEN	BIT(3)
49*91f16700Schasinglulu #define IMX_UART_CR2_TXEN	BIT(2)
50*91f16700Schasinglulu #define IMX_UART_CR2_RXEN	BIT(1)
51*91f16700Schasinglulu #define IMX_UART_CR2_SRST	BIT(0)
52*91f16700Schasinglulu 
53*91f16700Schasinglulu #define IMX_UART_CR3_OFFSET	0x88
54*91f16700Schasinglulu #define IMX_UART_CR3_DTREN	BIT(13)
55*91f16700Schasinglulu #define IMX_UART_CR3_PARERREN	BIT(12)
56*91f16700Schasinglulu #define IMX_UART_CR3_FARERREN	BIT(11)
57*91f16700Schasinglulu #define IMX_UART_CR3_DSD	BIT(10)
58*91f16700Schasinglulu #define IMX_UART_CR3_DCD	BIT(9)
59*91f16700Schasinglulu #define IMX_UART_CR3_RI		BIT(8)
60*91f16700Schasinglulu #define IMX_UART_CR3_ADNIMP	BIT(7)
61*91f16700Schasinglulu #define IMX_UART_CR3_RXDSEN	BIT(6)
62*91f16700Schasinglulu #define IMX_UART_CR3_AIRINTEN	BIT(5)
63*91f16700Schasinglulu #define IMX_UART_CR3_AWAKEN	BIT(4)
64*91f16700Schasinglulu #define IMX_UART_CR3_DTRDEN	BIT(3)
65*91f16700Schasinglulu #define IMX_UART_CR3_RXDMUXSEL	BIT(2)
66*91f16700Schasinglulu #define IMX_UART_CR3_INVT	BIT(1)
67*91f16700Schasinglulu #define IMX_UART_CR3_ACIEN	BIT(0)
68*91f16700Schasinglulu 
69*91f16700Schasinglulu #define IMX_UART_CR4_OFFSET	0x8c
70*91f16700Schasinglulu #define IMX_UART_CR4_INVR	BIT(9)
71*91f16700Schasinglulu #define IMX_UART_CR4_ENIRI	BIT(8)
72*91f16700Schasinglulu #define IMX_UART_CR4_WKEN	BIT(7)
73*91f16700Schasinglulu #define IMX_UART_CR4_IDDMAEN	BIT(6)
74*91f16700Schasinglulu #define IMX_UART_CR4_IRSC	BIT(5)
75*91f16700Schasinglulu #define IMX_UART_CR4_LPBYP	BIT(4)
76*91f16700Schasinglulu #define IMX_UART_CR4_TCEN	BIT(3)
77*91f16700Schasinglulu #define IMX_UART_CR4_BKEN	BIT(2)
78*91f16700Schasinglulu #define IMX_UART_CR4_OREN	BIT(1)
79*91f16700Schasinglulu #define IMX_UART_CR4_DREN	BIT(0)
80*91f16700Schasinglulu 
81*91f16700Schasinglulu #define IMX_UART_FCR_OFFSET	0x90
82*91f16700Schasinglulu #define IMX_UART_FCR_TXTL_MASK	(BIT(15) | BIT(14) | BIT(13) | BIT(12) |\
83*91f16700Schasinglulu 				 BIT(11) | BIT(10))
84*91f16700Schasinglulu #define IMX_UART_FCR_TXTL(x)	((x) << 10)
85*91f16700Schasinglulu #define IMX_UART_FCR_RFDIV_MASK	(BIT(9) | BIT(8) | BIT(7))
86*91f16700Schasinglulu #define IMX_UART_FCR_RFDIV7	(BIT(9) | BIT(8))
87*91f16700Schasinglulu #define IMX_UART_FCR_RFDIV1	(BIT(9) | BIT(7))
88*91f16700Schasinglulu #define IMX_UART_FCR_RFDIV2	BIT(9)
89*91f16700Schasinglulu #define IMX_UART_FCR_RFDIV3	(BIT(8) | BIT(7))
90*91f16700Schasinglulu #define IMX_UART_FCR_RFDIV4	BIT(8)
91*91f16700Schasinglulu #define IMX_UART_FCR_RFDIV5	BIT(7)
92*91f16700Schasinglulu #define IMX_UART_FCR_RFDIV6	0
93*91f16700Schasinglulu #define IMX_UART_FCR_DCEDTE	BIT(6)
94*91f16700Schasinglulu #define IMX_UART_FCR_RXTL_MASK	(BIT(5) | BIT(4) | BIT(3) | BIT(2) |\
95*91f16700Schasinglulu 				 BIT(1) | BIT(0))
96*91f16700Schasinglulu #define IMX_UART_FCR_RXTL(x)	x
97*91f16700Schasinglulu 
98*91f16700Schasinglulu #define IMX_UART_STAT1_OFFSET	0x94
99*91f16700Schasinglulu #define IMX_UART_STAT1_PARITYERR	BIT(15)
100*91f16700Schasinglulu #define IMX_UART_STAT1_RTSS	BIT(14)
101*91f16700Schasinglulu #define IMX_UART_STAT1_TRDY	BIT(13)
102*91f16700Schasinglulu #define IMX_UART_STAT1_RTSD	BIT(12)
103*91f16700Schasinglulu #define IMX_UART_STAT1_ESCF	BIT(11)
104*91f16700Schasinglulu #define IMX_UART_STAT1_FRAMEERR	BIT(10)
105*91f16700Schasinglulu #define IMX_UART_STAT1_RRDY	BIT(9)
106*91f16700Schasinglulu #define IMX_UART_STAT1_AGTIM	BIT(8)
107*91f16700Schasinglulu #define IMX_UART_STAT1_DTRD	BIT(7)
108*91f16700Schasinglulu #define IMX_UART_STAT1_RXDS	BIT(6)
109*91f16700Schasinglulu #define IMX_UART_STAT1_AIRINT	BIT(5)
110*91f16700Schasinglulu #define IMX_UART_STAT1_AWAKE	BIT(4)
111*91f16700Schasinglulu #define IMX_UART_STAT1_SAD	BIT(3)
112*91f16700Schasinglulu 
113*91f16700Schasinglulu #define IMX_UART_STAT2_OFFSET	0x98
114*91f16700Schasinglulu #define IMX_UART_STAT2_ADET	BIT(15)
115*91f16700Schasinglulu #define IMX_UART_STAT2_TXFE	BIT(14)
116*91f16700Schasinglulu #define IMX_UART_STAT2_DTRF	BIT(13)
117*91f16700Schasinglulu #define IMX_UART_STAT2_IDLE	BIT(12)
118*91f16700Schasinglulu #define IMX_UART_STAT2_ACST	BIT(11)
119*91f16700Schasinglulu #define IMX_UART_STAT2_RIDELT	BIT(10)
120*91f16700Schasinglulu #define IMX_UART_STAT2_RIIN	BIT(9)
121*91f16700Schasinglulu #define IMX_UART_STAT2_IRINT	BIT(8)
122*91f16700Schasinglulu #define IMX_UART_STAT2_WAKE	BIT(7)
123*91f16700Schasinglulu #define IMX_UART_STAT2_DCDDELT	BIT(6)
124*91f16700Schasinglulu #define IMX_UART_STAT2_DCDIN	BIT(5)
125*91f16700Schasinglulu #define IMX_UART_STAT2_RTSF	BIT(4)
126*91f16700Schasinglulu #define IMX_UART_STAT2_TXDC	BIT(3)
127*91f16700Schasinglulu #define IMX_UART_STAT2_BRCD	BIT(2)
128*91f16700Schasinglulu #define IMX_UART_STAT2_ORE	BIT(1)
129*91f16700Schasinglulu #define IMX_UART_STAT2_RCR	BIT(0)
130*91f16700Schasinglulu 
131*91f16700Schasinglulu #define IMX_UART_ESC_OFFSET	0x9c
132*91f16700Schasinglulu 
133*91f16700Schasinglulu #define IMX_UART_TIM_OFFSET	0xa0
134*91f16700Schasinglulu 
135*91f16700Schasinglulu #define IMX_UART_BIR_OFFSET	0xa4
136*91f16700Schasinglulu 
137*91f16700Schasinglulu #define IMX_UART_BMR_OFFSET	0xa8
138*91f16700Schasinglulu 
139*91f16700Schasinglulu #define IMX_UART_BRC_OFFSET	0xac
140*91f16700Schasinglulu 
141*91f16700Schasinglulu #define IMX_UART_ONEMS_OFFSET	0xb0
142*91f16700Schasinglulu 
143*91f16700Schasinglulu #define IMX_UART_TS_OFFSET	0xb4
144*91f16700Schasinglulu #define IMX_UART_TS_FRCPERR	BIT(13)
145*91f16700Schasinglulu #define IMX_UART_TS_LOOP	BIT(12)
146*91f16700Schasinglulu #define IMX_UART_TS_DBGEN	BIT(11)
147*91f16700Schasinglulu #define IMX_UART_TS_LOOPIR	BIT(10)
148*91f16700Schasinglulu #define IMX_UART_TS_RXDBG	BIT(9)
149*91f16700Schasinglulu #define IMX_UART_TS_TXEMPTY	BIT(6)
150*91f16700Schasinglulu #define IMX_UART_TS_RXEMPTY	BIT(5)
151*91f16700Schasinglulu #define IMX_UART_TS_TXFULL	BIT(4)
152*91f16700Schasinglulu #define IMX_UART_TS_RXFULL	BIT(3)
153*91f16700Schasinglulu #define IMX_UART_TS_SOFTRST	BIT(0)
154*91f16700Schasinglulu 
155*91f16700Schasinglulu #ifndef __ASSEMBLER__
156*91f16700Schasinglulu 
157*91f16700Schasinglulu int console_imx_uart_register(uintptr_t baseaddr,
158*91f16700Schasinglulu 			      uint32_t clock,
159*91f16700Schasinglulu 			      uint32_t baud,
160*91f16700Schasinglulu 			      console_t *console);
161*91f16700Schasinglulu #endif /*__ASSEMBLER__*/
162*91f16700Schasinglulu 
163*91f16700Schasinglulu #endif /* IMX_UART_H */
164