1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #include <assert.h> 8*91f16700Schasinglulu 9*91f16700Schasinglulu #include <drivers/arm/sp804_delay_timer.h> 10*91f16700Schasinglulu #include <drivers/delay_timer.h> 11*91f16700Schasinglulu #include <lib/mmio.h> 12*91f16700Schasinglulu 13*91f16700Schasinglulu uintptr_t sp804_base_addr; 14*91f16700Schasinglulu 15*91f16700Schasinglulu #define SP804_TIMER1_LOAD (sp804_base_addr + 0x000) 16*91f16700Schasinglulu #define SP804_TIMER1_VALUE (sp804_base_addr + 0x004) 17*91f16700Schasinglulu #define SP804_TIMER1_CONTROL (sp804_base_addr + 0x008) 18*91f16700Schasinglulu #define SP804_TIMER1_BGLOAD (sp804_base_addr + 0x018) 19*91f16700Schasinglulu 20*91f16700Schasinglulu #define TIMER_CTRL_ONESHOT (1 << 0) 21*91f16700Schasinglulu #define TIMER_CTRL_32BIT (1 << 1) 22*91f16700Schasinglulu #define TIMER_CTRL_DIV1 (0 << 2) 23*91f16700Schasinglulu #define TIMER_CTRL_DIV16 (1 << 2) 24*91f16700Schasinglulu #define TIMER_CTRL_DIV256 (2 << 2) 25*91f16700Schasinglulu #define TIMER_CTRL_IE (1 << 5) 26*91f16700Schasinglulu #define TIMER_CTRL_PERIODIC (1 << 6) 27*91f16700Schasinglulu #define TIMER_CTRL_ENABLE (1 << 7) 28*91f16700Schasinglulu 29*91f16700Schasinglulu /******************************************************************** 30*91f16700Schasinglulu * The SP804 timer delay function 31*91f16700Schasinglulu ********************************************************************/ 32*91f16700Schasinglulu uint32_t sp804_get_timer_value(void) 33*91f16700Schasinglulu { 34*91f16700Schasinglulu return mmio_read_32(SP804_TIMER1_VALUE); 35*91f16700Schasinglulu } 36*91f16700Schasinglulu 37*91f16700Schasinglulu /******************************************************************** 38*91f16700Schasinglulu * Initialize the 1st timer in the SP804 dual timer with a base 39*91f16700Schasinglulu * address and a timer ops 40*91f16700Schasinglulu ********************************************************************/ 41*91f16700Schasinglulu void sp804_timer_ops_init(uintptr_t base_addr, const timer_ops_t *ops) 42*91f16700Schasinglulu { 43*91f16700Schasinglulu assert(base_addr != 0); 44*91f16700Schasinglulu assert(ops != 0 && ops->get_timer_value == sp804_get_timer_value); 45*91f16700Schasinglulu 46*91f16700Schasinglulu sp804_base_addr = base_addr; 47*91f16700Schasinglulu timer_init(ops); 48*91f16700Schasinglulu 49*91f16700Schasinglulu /* disable timer1 */ 50*91f16700Schasinglulu mmio_write_32(SP804_TIMER1_CONTROL, 0); 51*91f16700Schasinglulu mmio_write_32(SP804_TIMER1_LOAD, UINT32_MAX); 52*91f16700Schasinglulu mmio_write_32(SP804_TIMER1_VALUE, UINT32_MAX); 53*91f16700Schasinglulu 54*91f16700Schasinglulu /* enable as a free running 32-bit counter */ 55*91f16700Schasinglulu mmio_write_32(SP804_TIMER1_CONTROL, 56*91f16700Schasinglulu TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE); 57*91f16700Schasinglulu } 58