1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2019, Arm Limited. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #include <assert.h> 8*91f16700Schasinglulu #include <drivers/arm/scu.h> 9*91f16700Schasinglulu #include <lib/mmio.h> 10*91f16700Schasinglulu #include <plat/common/platform.h> 11*91f16700Schasinglulu #include <stdint.h> 12*91f16700Schasinglulu 13*91f16700Schasinglulu /******************************************************************************* 14*91f16700Schasinglulu * Turn ON snoop control unit. This is needed to synchronize the data between 15*91f16700Schasinglulu * CPU's. 16*91f16700Schasinglulu ******************************************************************************/ 17*91f16700Schasinglulu void enable_snoop_ctrl_unit(uintptr_t base) 18*91f16700Schasinglulu { 19*91f16700Schasinglulu uint32_t scu_ctrl; 20*91f16700Schasinglulu 21*91f16700Schasinglulu INFO("[SCU]: enabling snoop control unit ... \n"); 22*91f16700Schasinglulu 23*91f16700Schasinglulu assert(base != 0U); 24*91f16700Schasinglulu scu_ctrl = mmio_read_32(base + SCU_CTRL_REG); 25*91f16700Schasinglulu 26*91f16700Schasinglulu /* already enabled? */ 27*91f16700Schasinglulu if ((scu_ctrl & SCU_ENABLE_BIT) != 0) { 28*91f16700Schasinglulu return; 29*91f16700Schasinglulu } 30*91f16700Schasinglulu 31*91f16700Schasinglulu scu_ctrl |= SCU_ENABLE_BIT; 32*91f16700Schasinglulu mmio_write_32(base + SCU_CTRL_REG, scu_ctrl); 33*91f16700Schasinglulu } 34*91f16700Schasinglulu 35*91f16700Schasinglulu /******************************************************************************* 36*91f16700Schasinglulu * Snoop Control Unit configuration register. This is read-only register and 37*91f16700Schasinglulu * contains information such as 38*91f16700Schasinglulu * - number of CPUs present 39*91f16700Schasinglulu * - is a particular CPU operating in SMP mode or AMP mode 40*91f16700Schasinglulu * - data cache size of a particular CPU 41*91f16700Schasinglulu * - does SCU has ACP port 42*91f16700Schasinglulu * - is L2CPRESENT 43*91f16700Schasinglulu * NOTE: user of this API should interpert the bits in this register according 44*91f16700Schasinglulu * to the TRM 45*91f16700Schasinglulu ******************************************************************************/ 46*91f16700Schasinglulu uint32_t read_snoop_ctrl_unit_cfg(uintptr_t base) 47*91f16700Schasinglulu { 48*91f16700Schasinglulu assert(base != 0U); 49*91f16700Schasinglulu 50*91f16700Schasinglulu return mmio_read_32(base + SCU_CFG_REG); 51*91f16700Schasinglulu } 52