1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2019-2023, Arm Limited. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #include <assert.h> 8*91f16700Schasinglulu #include <stdint.h> 9*91f16700Schasinglulu #include <drivers/arm/sbsa.h> 10*91f16700Schasinglulu #include <lib/mmio.h> 11*91f16700Schasinglulu #include <plat/common/platform.h> 12*91f16700Schasinglulu 13*91f16700Schasinglulu void sbsa_watchdog_offset_reg_write(uintptr_t base, uint64_t value) 14*91f16700Schasinglulu { 15*91f16700Schasinglulu assert((value >> SBSA_WDOG_WOR_WIDTH) == 0); 16*91f16700Schasinglulu mmio_write_32(base + SBSA_WDOG_WOR_LOW_OFFSET, 17*91f16700Schasinglulu ((uint32_t)value & UINT32_MAX)); 18*91f16700Schasinglulu mmio_write_32(base + SBSA_WDOG_WOR_HIGH_OFFSET, (uint32_t)(value >> 32)); 19*91f16700Schasinglulu } 20*91f16700Schasinglulu 21*91f16700Schasinglulu /* 22*91f16700Schasinglulu * Start the watchdog timer at base address "base" for a 23*91f16700Schasinglulu * period of "ms" milliseconds.The watchdog has to be 24*91f16700Schasinglulu * refreshed within this time period. 25*91f16700Schasinglulu */ 26*91f16700Schasinglulu void sbsa_wdog_start(uintptr_t base, uint64_t ms) 27*91f16700Schasinglulu { 28*91f16700Schasinglulu uint64_t counter_freq; 29*91f16700Schasinglulu uint64_t offset_reg_value; 30*91f16700Schasinglulu 31*91f16700Schasinglulu counter_freq = (uint64_t)plat_get_syscnt_freq2(); 32*91f16700Schasinglulu offset_reg_value = ms * counter_freq / 1000; 33*91f16700Schasinglulu 34*91f16700Schasinglulu sbsa_watchdog_offset_reg_write(base, offset_reg_value); 35*91f16700Schasinglulu mmio_write_32(base + SBSA_WDOG_WCS_OFFSET, SBSA_WDOG_WCS_EN); 36*91f16700Schasinglulu } 37*91f16700Schasinglulu 38*91f16700Schasinglulu /* Stop the watchdog */ 39*91f16700Schasinglulu void sbsa_wdog_stop(uintptr_t base) 40*91f16700Schasinglulu { 41*91f16700Schasinglulu mmio_write_32(base + SBSA_WDOG_WCS_OFFSET, (0x0)); 42*91f16700Schasinglulu } 43*91f16700Schasinglulu 44*91f16700Schasinglulu /* Refresh the secure watchdog timer explicitly */ 45*91f16700Schasinglulu void sbsa_wdog_refresh(uintptr_t refresh_base) 46*91f16700Schasinglulu { 47*91f16700Schasinglulu mmio_write_32(refresh_base + SBSA_WDOG_WRR_OFFSET, SBSA_WDOG_WRR_REFRESH); 48*91f16700Schasinglulu } 49