1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2020-2022, Arm Limited. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef MHU_V2_X_H 8*91f16700Schasinglulu #define MHU_V2_X_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #include <stdbool.h> 11*91f16700Schasinglulu #include <stdint.h> 12*91f16700Schasinglulu 13*91f16700Schasinglulu #define MHU_2_X_INTR_NR2R_OFF (0x0u) 14*91f16700Schasinglulu #define MHU_2_X_INTR_R2NR_OFF (0x1u) 15*91f16700Schasinglulu #define MHU_2_1_INTR_CHCOMB_OFF (0x2u) 16*91f16700Schasinglulu 17*91f16700Schasinglulu #define MHU_2_X_INTR_NR2R_MASK (0x1u << MHU_2_X_INTR_NR2R_OFF) 18*91f16700Schasinglulu #define MHU_2_X_INTR_R2NR_MASK (0x1u << MHU_2_X_INTR_R2NR_OFF) 19*91f16700Schasinglulu #define MHU_2_1_INTR_CHCOMB_MASK (0x1u << MHU_2_1_INTR_CHCOMB_OFF) 20*91f16700Schasinglulu 21*91f16700Schasinglulu enum mhu_v2_x_frame_t { 22*91f16700Schasinglulu MHU_V2_X_SENDER_FRAME = 0x0u, 23*91f16700Schasinglulu MHU_V2_X_RECEIVER_FRAME = 0x1u, 24*91f16700Schasinglulu }; 25*91f16700Schasinglulu 26*91f16700Schasinglulu enum mhu_v2_x_supported_revisions { 27*91f16700Schasinglulu MHU_REV_READ_FROM_HW = 0, 28*91f16700Schasinglulu MHU_REV_2_0, 29*91f16700Schasinglulu MHU_REV_2_1, 30*91f16700Schasinglulu }; 31*91f16700Schasinglulu 32*91f16700Schasinglulu struct mhu_v2_x_dev_t { 33*91f16700Schasinglulu uintptr_t base; 34*91f16700Schasinglulu enum mhu_v2_x_frame_t frame; 35*91f16700Schasinglulu uint32_t subversion; /*!< Hardware subversion: v2.X */ 36*91f16700Schasinglulu bool is_initialized; /*!< Indicates if the MHU driver 37*91f16700Schasinglulu * is initialized and enabled 38*91f16700Schasinglulu */ 39*91f16700Schasinglulu }; 40*91f16700Schasinglulu 41*91f16700Schasinglulu /** 42*91f16700Schasinglulu * MHU v2 error enumeration types. 43*91f16700Schasinglulu */ 44*91f16700Schasinglulu enum mhu_v2_x_error_t { 45*91f16700Schasinglulu MHU_V_2_X_ERR_NONE = 0, 46*91f16700Schasinglulu MHU_V_2_X_ERR_NOT_INIT = -1, 47*91f16700Schasinglulu MHU_V_2_X_ERR_ALREADY_INIT = -2, 48*91f16700Schasinglulu MHU_V_2_X_ERR_UNSUPPORTED_VERSION = -3, 49*91f16700Schasinglulu MHU_V_2_X_ERR_INVALID_ARG = -4, 50*91f16700Schasinglulu MHU_V_2_X_ERR_GENERAL = -5 51*91f16700Schasinglulu }; 52*91f16700Schasinglulu 53*91f16700Schasinglulu /** 54*91f16700Schasinglulu * Initializes the driver. 55*91f16700Schasinglulu * 56*91f16700Schasinglulu * dev MHU device struct mhu_v2_x_dev_t. 57*91f16700Schasinglulu * rev MHU revision (if can't be identified from HW). 58*91f16700Schasinglulu * 59*91f16700Schasinglulu * Reads the MHU hardware version. 60*91f16700Schasinglulu * 61*91f16700Schasinglulu * Returns mhu_v2_x_error_t error code. 62*91f16700Schasinglulu * 63*91f16700Schasinglulu * MHU revision only has to be specified when versions can't be read 64*91f16700Schasinglulu * from HW (ARCH_MAJOR_REV reg reads as 0x0). 65*91f16700Schasinglulu * 66*91f16700Schasinglulu * This function doesn't check if dev is NULL. 67*91f16700Schasinglulu */ 68*91f16700Schasinglulu enum mhu_v2_x_error_t mhu_v2_x_driver_init(struct mhu_v2_x_dev_t *dev, 69*91f16700Schasinglulu enum mhu_v2_x_supported_revisions rev); 70*91f16700Schasinglulu 71*91f16700Schasinglulu /** 72*91f16700Schasinglulu * Returns the number of channels implemented. 73*91f16700Schasinglulu * 74*91f16700Schasinglulu * dev MHU device struct mhu_v2_x_dev_t. 75*91f16700Schasinglulu * 76*91f16700Schasinglulu * This function doesn't check if dev is NULL. 77*91f16700Schasinglulu */ 78*91f16700Schasinglulu uint32_t mhu_v2_x_get_num_channel_implemented( 79*91f16700Schasinglulu const struct mhu_v2_x_dev_t *dev); 80*91f16700Schasinglulu 81*91f16700Schasinglulu /** 82*91f16700Schasinglulu * Sends the value over a channel. 83*91f16700Schasinglulu * 84*91f16700Schasinglulu * dev MHU device struct mhu_v2_x_dev_t. 85*91f16700Schasinglulu * channel Channel to send the value over. 86*91f16700Schasinglulu * val Value to send. 87*91f16700Schasinglulu * 88*91f16700Schasinglulu * Sends the value over a channel. 89*91f16700Schasinglulu * 90*91f16700Schasinglulu * Returns mhu_v2_x_error_t error code. 91*91f16700Schasinglulu * 92*91f16700Schasinglulu * This function doesn't check if dev is NULL. 93*91f16700Schasinglulu * This function doesn't check if channel is implemented. 94*91f16700Schasinglulu */ 95*91f16700Schasinglulu enum mhu_v2_x_error_t mhu_v2_x_channel_send(const struct mhu_v2_x_dev_t *dev, 96*91f16700Schasinglulu uint32_t channel, uint32_t val); 97*91f16700Schasinglulu 98*91f16700Schasinglulu /** 99*91f16700Schasinglulu * Polls sender channel status. 100*91f16700Schasinglulu * 101*91f16700Schasinglulu * dev MHU device struct mhu_v2_x_dev_t. 102*91f16700Schasinglulu * channel Channel to poll the status of. 103*91f16700Schasinglulu * value Pointer to variable that will store the value. 104*91f16700Schasinglulu * 105*91f16700Schasinglulu * Polls sender channel status. 106*91f16700Schasinglulu * 107*91f16700Schasinglulu * Returns mhu_v2_x_error_t error code. 108*91f16700Schasinglulu * 109*91f16700Schasinglulu * This function doesn't check if dev is NULL. 110*91f16700Schasinglulu * This function doesn't check if channel is implemented. 111*91f16700Schasinglulu */ 112*91f16700Schasinglulu enum mhu_v2_x_error_t mhu_v2_x_channel_poll(const struct mhu_v2_x_dev_t *dev, 113*91f16700Schasinglulu uint32_t channel, uint32_t *value); 114*91f16700Schasinglulu 115*91f16700Schasinglulu /** 116*91f16700Schasinglulu * Clears the channel after the value is send over it. 117*91f16700Schasinglulu * 118*91f16700Schasinglulu * dev MHU device struct mhu_v2_x_dev_t. 119*91f16700Schasinglulu * channel Channel to clear. 120*91f16700Schasinglulu * 121*91f16700Schasinglulu * Clears the channel after the value is send over it. 122*91f16700Schasinglulu * 123*91f16700Schasinglulu * Returns mhu_v2_x_error_t error code.. 124*91f16700Schasinglulu * 125*91f16700Schasinglulu * This function doesn't check if dev is NULL. 126*91f16700Schasinglulu * This function doesn't check if channel is implemented. 127*91f16700Schasinglulu */ 128*91f16700Schasinglulu enum mhu_v2_x_error_t mhu_v2_x_channel_clear(const struct mhu_v2_x_dev_t *dev, 129*91f16700Schasinglulu uint32_t channel); 130*91f16700Schasinglulu 131*91f16700Schasinglulu /** 132*91f16700Schasinglulu * Receives the value over a channel. 133*91f16700Schasinglulu * 134*91f16700Schasinglulu * dev MHU device struct mhu_v2_x_dev_t. 135*91f16700Schasinglulu * channel Channel to receive the value from. 136*91f16700Schasinglulu * value Pointer to variable that will store the value. 137*91f16700Schasinglulu * 138*91f16700Schasinglulu * Receives the value over a channel. 139*91f16700Schasinglulu * 140*91f16700Schasinglulu * Returns mhu_v2_x_error_t error code. 141*91f16700Schasinglulu * 142*91f16700Schasinglulu * This function doesn't check if dev is NULL. 143*91f16700Schasinglulu * This function doesn't check if channel is implemented. 144*91f16700Schasinglulu */ 145*91f16700Schasinglulu enum mhu_v2_x_error_t mhu_v2_x_channel_receive( 146*91f16700Schasinglulu const struct mhu_v2_x_dev_t *dev, uint32_t channel, uint32_t *value); 147*91f16700Schasinglulu 148*91f16700Schasinglulu /** 149*91f16700Schasinglulu * Sets bits in the Channel Mask. 150*91f16700Schasinglulu * 151*91f16700Schasinglulu * dev MHU device struct mhu_v2_x_dev_t. 152*91f16700Schasinglulu * channel Which channel's mask to set. 153*91f16700Schasinglulu * mask Mask to be set over a receiver frame. 154*91f16700Schasinglulu * 155*91f16700Schasinglulu * Sets bits in the Channel Mask. 156*91f16700Schasinglulu * 157*91f16700Schasinglulu * Returns mhu_v2_x_error_t error code.. 158*91f16700Schasinglulu * 159*91f16700Schasinglulu * This function doesn't check if dev is NULL. 160*91f16700Schasinglulu * This function doesn't check if channel is implemented. 161*91f16700Schasinglulu */ 162*91f16700Schasinglulu enum mhu_v2_x_error_t mhu_v2_x_channel_mask_set( 163*91f16700Schasinglulu const struct mhu_v2_x_dev_t *dev, uint32_t channel, uint32_t mask); 164*91f16700Schasinglulu 165*91f16700Schasinglulu /** 166*91f16700Schasinglulu * Clears bits in the Channel Mask. 167*91f16700Schasinglulu * 168*91f16700Schasinglulu * dev MHU device struct mhu_v2_x_dev_t. 169*91f16700Schasinglulu * channel Which channel's mask to clear. 170*91f16700Schasinglulu * mask Mask to be clear over a receiver frame. 171*91f16700Schasinglulu * 172*91f16700Schasinglulu * Clears bits in the Channel Mask. 173*91f16700Schasinglulu * 174*91f16700Schasinglulu * Returns mhu_v2_x_error_t error code. 175*91f16700Schasinglulu * 176*91f16700Schasinglulu * This function doesn't check if dev is NULL. 177*91f16700Schasinglulu * This function doesn't check if channel is implemented. 178*91f16700Schasinglulu */ 179*91f16700Schasinglulu enum mhu_v2_x_error_t mhu_v2_x_channel_mask_clear( 180*91f16700Schasinglulu const struct mhu_v2_x_dev_t *dev, uint32_t channel, uint32_t mask); 181*91f16700Schasinglulu 182*91f16700Schasinglulu /** 183*91f16700Schasinglulu * Initiates a MHU transfer with the handshake signals. 184*91f16700Schasinglulu * 185*91f16700Schasinglulu * dev MHU device struct mhu_v2_x_dev_t. 186*91f16700Schasinglulu * 187*91f16700Schasinglulu * Initiates a MHU transfer with the handshake signals in a blocking mode. 188*91f16700Schasinglulu * 189*91f16700Schasinglulu * Returns mhu_v2_x_error_t error code. 190*91f16700Schasinglulu * 191*91f16700Schasinglulu * This function doesn't check if dev is NULL. 192*91f16700Schasinglulu */ 193*91f16700Schasinglulu enum mhu_v2_x_error_t mhu_v2_x_initiate_transfer( 194*91f16700Schasinglulu const struct mhu_v2_x_dev_t *dev); 195*91f16700Schasinglulu 196*91f16700Schasinglulu /** 197*91f16700Schasinglulu * Closes a MHU transfer with the handshake signals. 198*91f16700Schasinglulu * 199*91f16700Schasinglulu * dev MHU device struct mhu_v2_x_dev_t. 200*91f16700Schasinglulu * 201*91f16700Schasinglulu * Closes a MHU transfer with the handshake signals in a blocking mode. 202*91f16700Schasinglulu * 203*91f16700Schasinglulu * Returns mhu_v2_x_error_t error code. 204*91f16700Schasinglulu * 205*91f16700Schasinglulu * This function doesn't check if dev is NULL. 206*91f16700Schasinglulu */ 207*91f16700Schasinglulu enum mhu_v2_x_error_t mhu_v2_x_close_transfer( 208*91f16700Schasinglulu const struct mhu_v2_x_dev_t *dev); 209*91f16700Schasinglulu 210*91f16700Schasinglulu #endif /* MHU_V2_X_H */ 211