1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #include <assert.h> 8*91f16700Schasinglulu 9*91f16700Schasinglulu #include <platform_def.h> 10*91f16700Schasinglulu 11*91f16700Schasinglulu #include <arch_helpers.h> 12*91f16700Schasinglulu #include <drivers/arm/css/css_mhu.h> 13*91f16700Schasinglulu #include <lib/bakery_lock.h> 14*91f16700Schasinglulu #include <lib/mmio.h> 15*91f16700Schasinglulu #include <plat/arm/common/plat_arm.h> 16*91f16700Schasinglulu 17*91f16700Schasinglulu /* SCP MHU secure channel registers */ 18*91f16700Schasinglulu #define SCP_INTR_S_STAT 0x200 19*91f16700Schasinglulu #define SCP_INTR_S_SET 0x208 20*91f16700Schasinglulu #define SCP_INTR_S_CLEAR 0x210 21*91f16700Schasinglulu 22*91f16700Schasinglulu /* CPU MHU secure channel registers */ 23*91f16700Schasinglulu #define CPU_INTR_S_STAT 0x300 24*91f16700Schasinglulu #define CPU_INTR_S_SET 0x308 25*91f16700Schasinglulu #define CPU_INTR_S_CLEAR 0x310 26*91f16700Schasinglulu 27*91f16700Schasinglulu ARM_INSTANTIATE_LOCK; 28*91f16700Schasinglulu 29*91f16700Schasinglulu /* Weak definition may be overridden in specific CSS based platform */ 30*91f16700Schasinglulu #pragma weak plat_arm_pwrc_setup 31*91f16700Schasinglulu 32*91f16700Schasinglulu 33*91f16700Schasinglulu /* 34*91f16700Schasinglulu * Slot 31 is reserved because the MHU hardware uses this register bit to 35*91f16700Schasinglulu * indicate a non-secure access attempt. The total number of available slots is 36*91f16700Schasinglulu * therefore 31 [30:0]. 37*91f16700Schasinglulu */ 38*91f16700Schasinglulu #define MHU_MAX_SLOT_ID 30 39*91f16700Schasinglulu 40*91f16700Schasinglulu void mhu_secure_message_start(unsigned int slot_id) 41*91f16700Schasinglulu { 42*91f16700Schasinglulu assert(slot_id <= MHU_MAX_SLOT_ID); 43*91f16700Schasinglulu 44*91f16700Schasinglulu arm_lock_get(); 45*91f16700Schasinglulu 46*91f16700Schasinglulu /* Make sure any previous command has finished */ 47*91f16700Schasinglulu while (mmio_read_32(PLAT_CSS_MHU_BASE + CPU_INTR_S_STAT) & 48*91f16700Schasinglulu (1 << slot_id)) 49*91f16700Schasinglulu ; 50*91f16700Schasinglulu } 51*91f16700Schasinglulu 52*91f16700Schasinglulu void mhu_secure_message_send(unsigned int slot_id) 53*91f16700Schasinglulu { 54*91f16700Schasinglulu assert(slot_id <= MHU_MAX_SLOT_ID); 55*91f16700Schasinglulu assert(!(mmio_read_32(PLAT_CSS_MHU_BASE + CPU_INTR_S_STAT) & 56*91f16700Schasinglulu (1 << slot_id))); 57*91f16700Schasinglulu 58*91f16700Schasinglulu /* Send command to SCP */ 59*91f16700Schasinglulu mmio_write_32(PLAT_CSS_MHU_BASE + CPU_INTR_S_SET, 1 << slot_id); 60*91f16700Schasinglulu } 61*91f16700Schasinglulu 62*91f16700Schasinglulu uint32_t mhu_secure_message_wait(void) 63*91f16700Schasinglulu { 64*91f16700Schasinglulu /* Wait for response from SCP */ 65*91f16700Schasinglulu uint32_t response; 66*91f16700Schasinglulu while (!(response = mmio_read_32(PLAT_CSS_MHU_BASE + SCP_INTR_S_STAT))) 67*91f16700Schasinglulu ; 68*91f16700Schasinglulu 69*91f16700Schasinglulu return response; 70*91f16700Schasinglulu } 71*91f16700Schasinglulu 72*91f16700Schasinglulu void mhu_secure_message_end(unsigned int slot_id) 73*91f16700Schasinglulu { 74*91f16700Schasinglulu assert(slot_id <= MHU_MAX_SLOT_ID); 75*91f16700Schasinglulu 76*91f16700Schasinglulu /* 77*91f16700Schasinglulu * Clear any response we got by writing one in the relevant slot bit to 78*91f16700Schasinglulu * the CLEAR register 79*91f16700Schasinglulu */ 80*91f16700Schasinglulu mmio_write_32(PLAT_CSS_MHU_BASE + SCP_INTR_S_CLEAR, 1 << slot_id); 81*91f16700Schasinglulu 82*91f16700Schasinglulu arm_lock_release(); 83*91f16700Schasinglulu } 84*91f16700Schasinglulu 85*91f16700Schasinglulu void __init mhu_secure_init(void) 86*91f16700Schasinglulu { 87*91f16700Schasinglulu arm_lock_init(); 88*91f16700Schasinglulu 89*91f16700Schasinglulu /* 90*91f16700Schasinglulu * The STAT register resets to zero. Ensure it is in the expected state, 91*91f16700Schasinglulu * as a stale or garbage value would make us think it's a message we've 92*91f16700Schasinglulu * already sent. 93*91f16700Schasinglulu */ 94*91f16700Schasinglulu assert(mmio_read_32(PLAT_CSS_MHU_BASE + CPU_INTR_S_STAT) == 0); 95*91f16700Schasinglulu } 96*91f16700Schasinglulu 97*91f16700Schasinglulu void __init plat_arm_pwrc_setup(void) 98*91f16700Schasinglulu { 99*91f16700Schasinglulu mhu_secure_init(); 100*91f16700Schasinglulu } 101