1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #include <drivers/allwinner/axp.h> 8*91f16700Schasinglulu 9*91f16700Schasinglulu const uint8_t axp_chip_id = AXP805_CHIP_ID; 10*91f16700Schasinglulu const char *const axp_compatible = "x-powers,axp805"; 11*91f16700Schasinglulu 12*91f16700Schasinglulu #if SUNXI_SETUP_REGULATORS == 1 13*91f16700Schasinglulu /* 14*91f16700Schasinglulu * The "dcdcd" split changes the step size by a factor of 5, not 2; 15*91f16700Schasinglulu * disallow values above the split to maintain accuracy. 16*91f16700Schasinglulu */ 17*91f16700Schasinglulu const struct axp_regulator axp_regulators[] = { 18*91f16700Schasinglulu {"dcdca", 600, 1520, 10, 50, 0x12, 0x10, 0}, 19*91f16700Schasinglulu {"dcdcb", 1000, 2550, 50, NA, 0x13, 0x10, 1}, 20*91f16700Schasinglulu {"dcdcc", 600, 1520, 10, 50, 0x14, 0x10, 2}, 21*91f16700Schasinglulu {"dcdcd", 600, 1500, 20, NA, 0x15, 0x10, 3}, 22*91f16700Schasinglulu {"dcdce", 1100, 3400, 100, NA, 0x16, 0x10, 4}, 23*91f16700Schasinglulu {"aldo1", 700, 3300, 100, NA, 0x17, 0x10, 5}, 24*91f16700Schasinglulu {"aldo2", 700, 3300, 100, NA, 0x18, 0x10, 6}, 25*91f16700Schasinglulu {"aldo3", 700, 3300, 100, NA, 0x19, 0x10, 7}, 26*91f16700Schasinglulu {"bldo1", 700, 1900, 100, NA, 0x20, 0x11, 0}, 27*91f16700Schasinglulu {"bldo2", 700, 1900, 100, NA, 0x21, 0x11, 1}, 28*91f16700Schasinglulu {"bldo3", 700, 1900, 100, NA, 0x22, 0x11, 2}, 29*91f16700Schasinglulu {"bldo4", 700, 1900, 100, NA, 0x23, 0x11, 3}, 30*91f16700Schasinglulu {"cldo1", 700, 3300, 100, NA, 0x24, 0x11, 4}, 31*91f16700Schasinglulu {"cldo2", 700, 4200, 100, 27, 0x25, 0x11, 5}, 32*91f16700Schasinglulu {"cldo3", 700, 3300, 100, NA, 0x26, 0x11, 6}, 33*91f16700Schasinglulu {} 34*91f16700Schasinglulu }; 35*91f16700Schasinglulu #endif 36