1*91f16700SchasingluluAdvisory TFV-5 (CVE-2017-15031) 2*91f16700Schasinglulu=============================== 3*91f16700Schasinglulu 4*91f16700Schasinglulu+----------------+-------------------------------------------------------------+ 5*91f16700Schasinglulu| Title | Not initializing or saving/restoring ``PMCR_EL0`` can leak | 6*91f16700Schasinglulu| | secure world timing information | 7*91f16700Schasinglulu+================+=============================================================+ 8*91f16700Schasinglulu| CVE ID | `CVE-2017-15031`_ | 9*91f16700Schasinglulu+----------------+-------------------------------------------------------------+ 10*91f16700Schasinglulu| Date | 02 Oct 2017, updated on 04 Nov 2019 | 11*91f16700Schasinglulu+----------------+-------------------------------------------------------------+ 12*91f16700Schasinglulu| Versions | All, up to and including v2.1 | 13*91f16700Schasinglulu| Affected | | 14*91f16700Schasinglulu+----------------+-------------------------------------------------------------+ 15*91f16700Schasinglulu| Configurations | All | 16*91f16700Schasinglulu| Affected | | 17*91f16700Schasinglulu+----------------+-------------------------------------------------------------+ 18*91f16700Schasinglulu| Impact | Leakage of sensitive secure world timing information | 19*91f16700Schasinglulu+----------------+-------------------------------------------------------------+ 20*91f16700Schasinglulu| Fix Version | `Pull Request #1127`_ (merged on 18 October 2017) | 21*91f16700Schasinglulu| | | 22*91f16700Schasinglulu| | `Commit e290a8fcbc`_ (merged on 23 August 2019) | 23*91f16700Schasinglulu| | | 24*91f16700Schasinglulu| | `Commit c3e8b0be9b`_ (merged on 27 September 2019) | 25*91f16700Schasinglulu+----------------+-------------------------------------------------------------+ 26*91f16700Schasinglulu| Credit | Arm, Marek Bykowski | 27*91f16700Schasinglulu+----------------+-------------------------------------------------------------+ 28*91f16700Schasinglulu 29*91f16700SchasingluluThe ``PMCR_EL0`` (Performance Monitors Control Register) provides details of the 30*91f16700SchasingluluPerformance Monitors implementation, including the number of counters 31*91f16700Schasingluluimplemented, and configures and controls the counters. If the ``PMCR_EL0.DP`` 32*91f16700Schasinglulubit is set to zero, the cycle counter (when enabled) counts during secure world 33*91f16700Schasingluluexecution, even when prohibited by the debug signals. 34*91f16700Schasinglulu 35*91f16700SchasingluluSince TF-A does not save and restore ``PMCR_EL0`` when switching between the 36*91f16700Schasinglulunormal and secure worlds, normal world code can set ``PMCR_EL0.DP`` to zero to 37*91f16700Schasinglulucause leakage of secure world timing information. This register should be added 38*91f16700Schasingluluto the list of saved/restored registers both when entering EL3 and also 39*91f16700Schasinglulutransitioning to S-EL1. 40*91f16700Schasinglulu 41*91f16700SchasingluluFurthermore, ``PMCR_EL0.DP`` has an architecturally ``UNKNOWN`` reset value. 42*91f16700SchasingluluSince Arm TF does not initialize this register, it's possible that on at least 43*91f16700Schasinglulusome implementations, ``PMCR_EL0.DP`` is set to zero by default. This and other 44*91f16700Schasinglulubits with an architecturally UNKNOWN reset value should be initialized to 45*91f16700Schasinglulusensible default values in the secure context. 46*91f16700Schasinglulu 47*91f16700SchasingluluThe same issue exists for the equivalent AArch32 register, ``PMCR``, except that 48*91f16700Schasingluluhere ``PMCR_EL0.DP`` architecturally resets to zero. 49*91f16700Schasinglulu 50*91f16700SchasingluluNOTE: The original pull request referenced above only fixed the issue for S-EL1 51*91f16700Schasingluluwhereas the EL3 was fixed in the later commits. 52*91f16700Schasinglulu 53*91f16700Schasinglulu.. _CVE-2017-15031: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2017-15031 54*91f16700Schasinglulu.. _Pull Request #1127: https://github.com/ARM-software/arm-trusted-firmware/pull/1127 55*91f16700Schasinglulu.. _Commit e290a8fcbc: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/commit/?id=e290a8fcbc 56*91f16700Schasinglulu.. _Commit c3e8b0be9b: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/commit/?id=c3e8b0be9b 57*91f16700Schasinglulu 58