1*91f16700SchasingluluSTM32 MPUs 2*91f16700Schasinglulu========== 3*91f16700Schasinglulu 4*91f16700SchasingluluSTM32 MPUs are microprocessors designed by STMicroelectronics 5*91f16700Schasinglulubased on Arm Cortex-A. This page presents the common configuration of STM32 6*91f16700SchasingluluMPUs, more details and dedicated configuration can be found in each STM32 MPU 7*91f16700Schasinglulupage (:ref:`STM32MP1` or :ref:`STM32MP2`) 8*91f16700Schasinglulu 9*91f16700SchasingluluDesign 10*91f16700Schasinglulu------ 11*91f16700SchasingluluThe STM32 MPU resets in the ROM code of the Cortex-A. 12*91f16700SchasingluluThe primary boot core (core 0) executes the boot sequence while 13*91f16700Schasinglulusecondary boot core (core 1) is kept in a holding pen loop. 14*91f16700SchasingluluThe ROM code boot sequence loads the TF-A binary image from boot device 15*91f16700Schasingluluto embedded SRAM. 16*91f16700Schasinglulu 17*91f16700SchasingluluThe TF-A image must be properly formatted with a STM32 header structure 18*91f16700Schasinglulufor ROM code is able to load this image. 19*91f16700SchasingluluTool stm32image can be used to prepend this header to the generated TF-A binary. 20*91f16700Schasinglulu 21*91f16700SchasingluluBoot 22*91f16700Schasinglulu~~~~ 23*91f16700SchasingluluOnly BL2 (with STM32 header) is loaded by ROM code. The other binaries are 24*91f16700Schasingluluinside the FIP binary: BL31 (for Aarch64 platforms), BL32 (OP-TEE), U-Boot 25*91f16700Schasingluluand their respective device tree blobs. 26*91f16700Schasinglulu 27*91f16700SchasingluluBoot sequence 28*91f16700Schasinglulu~~~~~~~~~~~~~ 29*91f16700Schasinglulu 30*91f16700SchasingluluROM code -> BL2 (compiled with RESET_TO_BL2) -> OP-TEE -> BL33 (U-Boot) 31*91f16700Schasinglulu 32*91f16700SchasingluluBuild Instructions 33*91f16700Schasinglulu------------------ 34*91f16700SchasingluluBoot media(s) supported by BL2 must be specified in the build command. 35*91f16700SchasingluluAvailable storage medias are: 36*91f16700Schasinglulu 37*91f16700Schasinglulu- ``STM32MP_SDMMC`` 38*91f16700Schasinglulu- ``STM32MP_EMMC`` 39*91f16700Schasinglulu- ``STM32MP_RAW_NAND`` 40*91f16700Schasinglulu- ``STM32MP_SPI_NAND`` 41*91f16700Schasinglulu- ``STM32MP_SPI_NOR`` 42*91f16700Schasinglulu 43*91f16700SchasingluluSerial boot devices: 44*91f16700Schasinglulu 45*91f16700Schasinglulu- ``STM32MP_UART_PROGRAMMER`` 46*91f16700Schasinglulu- ``STM32MP_USB_PROGRAMMER`` 47*91f16700Schasinglulu 48*91f16700Schasinglulu 49*91f16700SchasingluluOther configuration flags: 50*91f16700Schasinglulu 51*91f16700Schasinglulu- | ``DTB_FILE_NAME``: to precise board device-tree blob to be used. 52*91f16700Schasinglulu | Default: stm32mp157c-ev1.dtb 53*91f16700Schasinglulu- | ``DWL_BUFFER_BASE``: the 'serial boot' load address of FIP, 54*91f16700Schasinglulu | default location (end of the first 128MB) is used when absent 55*91f16700Schasinglulu- | ``STM32MP_EARLY_CONSOLE``: to enable early traces before clock driver is setup. 56*91f16700Schasinglulu | Default: 0 (disabled) 57*91f16700Schasinglulu- | ``STM32MP_RECONFIGURE_CONSOLE``: to re-configure crash console (especially after BL2). 58*91f16700Schasinglulu | Default: 0 (disabled) 59*91f16700Schasinglulu- | ``STM32MP_UART_BAUDRATE``: to select UART baud rate. 60*91f16700Schasinglulu | Default: 115200 61*91f16700Schasinglulu 62*91f16700Schasinglulu 63*91f16700SchasingluluPopulate SD-card 64*91f16700Schasinglulu---------------- 65*91f16700Schasinglulu 66*91f16700SchasingluluBoot with FIP 67*91f16700Schasinglulu~~~~~~~~~~~~~ 68*91f16700SchasingluluThe SD-card has to be formatted with GPT. 69*91f16700SchasingluluIt should contain at least those partitions: 70*91f16700Schasinglulu 71*91f16700Schasinglulu- fsbl: to copy the tf-a-stm32mp157c-ev1.stm32 binary (BL2) 72*91f16700Schasinglulu- fip (GUID 19d5df83-11b0-457b-be2c-7559c13142a5): which contains the FIP binary 73*91f16700Schasinglulu 74*91f16700SchasingluluUsually, two copies of fsbl are used (fsbl1 and fsbl2) instead of one partition fsbl. 75*91f16700Schasinglulu 76*91f16700Schasinglulu-------------- 77*91f16700Schasinglulu 78*91f16700Schasinglulu*Copyright (c) 2023, STMicroelectronics - All Rights Reserved* 79