1*91f16700SchasingluluMarvell IO WIN address decoding bindings 2*91f16700Schasinglulu======================================== 3*91f16700Schasinglulu 4*91f16700SchasingluluIO Window configuration driver (2nd stage address translation) for Marvell Armada 8K and 8K+ SoCs. 5*91f16700Schasinglulu 6*91f16700SchasingluluThe IO WIN includes a description of the address decoding configuration. 7*91f16700Schasinglulu 8*91f16700SchasingluluTransactions that are decoded by CCU windows as IO peripheral, have an additional 9*91f16700Schasinglululayer of decoding. This additional address decoding layer defines one of the 10*91f16700Schasinglulufollowing targets: 11*91f16700Schasinglulu 12*91f16700Schasinglulu- **0x0** = BootRom 13*91f16700Schasinglulu- **0x1** = STM (Serial Trace Macro-cell, a programmer's port into trace stream) 14*91f16700Schasinglulu- **0x2** = SPI direct access 15*91f16700Schasinglulu- **0x3** = PCIe registers 16*91f16700Schasinglulu- **0x4** = MCI Port 17*91f16700Schasinglulu- **0x5** = PCIe port 18*91f16700Schasinglulu 19*91f16700SchasingluluMandatory functions 20*91f16700Schasinglulu------------------- 21*91f16700Schasinglulu 22*91f16700Schasinglulu- marvell_get_io_win_memory_map 23*91f16700Schasinglulu Returns the IO windows configuration and the number of windows of the 24*91f16700Schasinglulu specific AP. 25*91f16700Schasinglulu 26*91f16700SchasingluluMandatory structures 27*91f16700Schasinglulu-------------------- 28*91f16700Schasinglulu 29*91f16700Schasinglulu- io_win_memory_map 30*91f16700Schasinglulu Array that include the configuration of the windows. Every window/entry is 31*91f16700Schasinglulu a struct which has 3 parameters: 32*91f16700Schasinglulu 33*91f16700Schasinglulu - Base address of the window 34*91f16700Schasinglulu - Size of the window 35*91f16700Schasinglulu - Target-ID of the window 36*91f16700Schasinglulu 37*91f16700SchasingluluExample 38*91f16700Schasinglulu------- 39*91f16700Schasinglulu 40*91f16700Schasinglulu.. code:: c 41*91f16700Schasinglulu 42*91f16700Schasinglulu struct addr_map_win io_win_memory_map[] = { 43*91f16700Schasinglulu {0x00000000fe000000, 0x000000001f00000, PCIE_PORT_TID}, /* PCIe window 31Mb for PCIe port*/ 44*91f16700Schasinglulu {0x00000000ffe00000, 0x000000000100000, PCIE_REGS_TID}, /* PCI-REG window 64Kb for PCIe-reg*/ 45*91f16700Schasinglulu {0x00000000f6000000, 0x000000000100000, MCIPHY_TID}, /* MCI window 1Mb for PHY-reg*/ 46*91f16700Schasinglulu }; 47