1*91f16700SchasingluluIntel Stratix 10 SoCFPGA 2*91f16700Schasinglulu======================== 3*91f16700Schasinglulu 4*91f16700SchasingluluStratix 10 SoCFPGA is a FPGA with integrated quad-core 64-bit Arm Cortex A53 processor. 5*91f16700Schasinglulu 6*91f16700SchasingluluUpon boot, Boot ROM loads bl2 into OCRAM. Bl2 subsequently initializes 7*91f16700Schasingluluthe hardware, then loads bl31 and bl33 (UEFI) into DDR and boots to bl33. 8*91f16700Schasinglulu 9*91f16700Schasinglulu:: 10*91f16700Schasinglulu 11*91f16700Schasinglulu Boot ROM --> Trusted Firmware-A --> UEFI 12*91f16700Schasinglulu 13*91f16700SchasingluluHow to build 14*91f16700Schasinglulu------------ 15*91f16700Schasinglulu 16*91f16700SchasingluluCode Locations 17*91f16700Schasinglulu~~~~~~~~~~~~~~ 18*91f16700Schasinglulu 19*91f16700Schasinglulu- Trusted Firmware-A: 20*91f16700Schasinglulu `link <https://github.com/ARM-software/arm-trusted-firmware>`__ 21*91f16700Schasinglulu 22*91f16700Schasinglulu- UEFI (to be updated with new upstreamed UEFI): 23*91f16700Schasinglulu `link <https://github.com/altera-opensource/uefi-socfpga>`__ 24*91f16700Schasinglulu 25*91f16700SchasingluluBuild Procedure 26*91f16700Schasinglulu~~~~~~~~~~~~~~~ 27*91f16700Schasinglulu 28*91f16700Schasinglulu- Fetch all the above 2 repositories into local host. 29*91f16700Schasinglulu Make all the repositories in the same ${BUILD\_PATH}. 30*91f16700Schasinglulu 31*91f16700Schasinglulu- Prepare the AARCH64 toolchain. 32*91f16700Schasinglulu 33*91f16700Schasinglulu- Build UEFI using Stratix 10 platform as configuration 34*91f16700Schasinglulu This will be updated to use an updated UEFI using the latest EDK2 source 35*91f16700Schasinglulu 36*91f16700Schasinglulu.. code:: bash 37*91f16700Schasinglulu 38*91f16700Schasinglulu make CROSS_COMPILE=aarch64-linux-gnu- device=s10 39*91f16700Schasinglulu 40*91f16700Schasinglulu- Build atf providing the previously generated UEFI as the BL33 image 41*91f16700Schasinglulu 42*91f16700Schasinglulu.. code:: bash 43*91f16700Schasinglulu 44*91f16700Schasinglulu make CROSS_COMPILE=aarch64-linux-gnu- bl2 fip PLAT=stratix10 45*91f16700Schasinglulu BL33=PEI.ROM 46*91f16700Schasinglulu 47*91f16700SchasingluluInstall Procedure 48*91f16700Schasinglulu~~~~~~~~~~~~~~~~~ 49*91f16700Schasinglulu 50*91f16700Schasinglulu- dd fip.bin to a A2 partition on the MMC drive to be booted in Stratix 10 51*91f16700Schasinglulu board. 52*91f16700Schasinglulu 53*91f16700Schasinglulu- Generate a SOF containing bl2 54*91f16700Schasinglulu 55*91f16700Schasinglulu.. code:: bash 56*91f16700Schasinglulu 57*91f16700Schasinglulu aarch64-linux-gnu-objcopy -I binary -O ihex --change-addresses 0xffe00000 bl2.bin bl2.hex 58*91f16700Schasinglulu quartus_cpf --bootloader bl2.hex <quartus_generated_sof> <output_sof_with_bl2> 59*91f16700Schasinglulu 60*91f16700Schasinglulu- Configure SOF to board 61*91f16700Schasinglulu 62*91f16700Schasinglulu.. code:: bash 63*91f16700Schasinglulu 64*91f16700Schasinglulu nios2-configure-sof <output_sof_with_bl2> 65*91f16700Schasinglulu 66*91f16700SchasingluluBoot trace 67*91f16700Schasinglulu---------- 68*91f16700Schasinglulu 69*91f16700Schasinglulu:: 70*91f16700Schasinglulu 71*91f16700Schasinglulu INFO: DDR: DRAM calibration success. 72*91f16700Schasinglulu INFO: ECC is disabled. 73*91f16700Schasinglulu INFO: Init HPS NOC's DDR Scheduler. 74*91f16700Schasinglulu NOTICE: BL2: v2.0(debug):v2.0-809-g7f8474a-dirty 75*91f16700Schasinglulu NOTICE: BL2: Built : 17:38:19, Feb 18 2019 76*91f16700Schasinglulu INFO: BL2: Doing platform setup 77*91f16700Schasinglulu INFO: BL2: Loading image id 3 78*91f16700Schasinglulu INFO: Loading image id=3 at address 0xffe1c000 79*91f16700Schasinglulu INFO: Image id=3 loaded: 0xffe1c000 - 0xffe24034 80*91f16700Schasinglulu INFO: BL2: Loading image id 5 81*91f16700Schasinglulu INFO: Loading image id=5 at address 0x50000 82*91f16700Schasinglulu INFO: Image id=5 loaded: 0x50000 - 0x550000 83*91f16700Schasinglulu NOTICE: BL2: Booting BL31 84*91f16700Schasinglulu INFO: Entry point address = 0xffe1c000 85*91f16700Schasinglulu INFO: SPSR = 0x3cd 86*91f16700Schasinglulu NOTICE: BL31: v2.0(debug):v2.0-810-g788c436-dirty 87*91f16700Schasinglulu NOTICE: BL31: Built : 15:17:16, Feb 20 2019 88*91f16700Schasinglulu INFO: ARM GICv2 driver initialized 89*91f16700Schasinglulu INFO: BL31: Initializing runtime services 90*91f16700Schasinglulu WARNING: BL31: cortex_a53: CPU workaround for 855873 was missing! 91*91f16700Schasinglulu INFO: BL31: Preparing for EL3 exit to normal world 92*91f16700Schasinglulu INFO: Entry point address = 0x50000 93*91f16700Schasinglulu INFO: SPSR = 0x3c9 94*91f16700Schasinglulu UEFI firmware (version 1.0 built at 11:26:18 on Nov 7 2018) 95