1*91f16700SchasingluluNXP i.MX 8M Series 2*91f16700Schasinglulu================== 3*91f16700Schasinglulu 4*91f16700SchasingluluThe i.MX 8M family of applications processors based on Arm Corte-A53 and Cortex-M4 5*91f16700Schasinglulucores provide high-performance computing, power efficiency, enhanced system 6*91f16700Schasinglulureliability and embedded security needed to drive the growth of fast-growing 7*91f16700Schasingluluedge node computing, streaming multimedia, and machine learning applications. 8*91f16700Schasinglulu 9*91f16700Schasingluluimx8mq is dropped in TF-A CI build due to the small OCRAM size, but still actively 10*91f16700Schasinglulumaintained in NXP official release. 11*91f16700Schasinglulu 12*91f16700SchasingluluBoot Sequence 13*91f16700Schasinglulu------------- 14*91f16700Schasinglulu 15*91f16700SchasingluluBootrom --> SPL --> BL31 --> BL33(u-boot) --> Linux kernel 16*91f16700Schasinglulu 17*91f16700SchasingluluHow to build 18*91f16700Schasinglulu------------ 19*91f16700Schasinglulu 20*91f16700SchasingluluBuild Procedure 21*91f16700Schasinglulu~~~~~~~~~~~~~~~ 22*91f16700Schasinglulu 23*91f16700Schasinglulu- Prepare AARCH64 toolchain. 24*91f16700Schasinglulu 25*91f16700Schasinglulu- Build spl and u-boot firstly, and get binary images: u-boot-spl.bin, 26*91f16700Schasinglulu u-boot-nodtb.bin and dtb for the target board. 27*91f16700Schasinglulu 28*91f16700Schasinglulu- Build TF-A 29*91f16700Schasinglulu 30*91f16700Schasinglulu Build bl31: 31*91f16700Schasinglulu 32*91f16700Schasinglulu .. code:: shell 33*91f16700Schasinglulu 34*91f16700Schasinglulu CROSS_COMPILE=aarch64-linux-gnu- make PLAT=<Target_SoC> bl31 35*91f16700Schasinglulu 36*91f16700Schasinglulu Target_SoC should be "imx8mq" for i.MX8MQ SoC. 37*91f16700Schasinglulu Target_SoC should be "imx8mm" for i.MX8MM SoC. 38*91f16700Schasinglulu Target_SoC should be "imx8mn" for i.MX8MN SoC. 39*91f16700Schasinglulu Target_SoC should be "imx8mp" for i.MX8MP SoC. 40*91f16700Schasinglulu 41*91f16700SchasingluluDeploy TF-A Images 42*91f16700Schasinglulu~~~~~~~~~~~~~~~~~~ 43*91f16700Schasinglulu 44*91f16700SchasingluluTF-A binary(bl31.bin), u-boot-spl.bin u-boot-nodtb.bin and dtb are combined 45*91f16700Schasinglulutogether to generate a binary file called flash.bin, the imx-mkimage tool is 46*91f16700Schasingluluused to generate flash.bin, and flash.bin needs to be flashed into SD card 47*91f16700Schasingluluwith certain offset for BOOT ROM. the u-boot and imx-mkimage will be upstreamed 48*91f16700Schasinglulusoon, this doc will be updated once they are ready, and the link will be posted. 49*91f16700Schasinglulu 50*91f16700SchasingluluTBBR Boot Sequence 51*91f16700Schasinglulu------------------ 52*91f16700Schasinglulu 53*91f16700SchasingluluWhen setting NEED_BL2=1 on imx8mm. We support an alternative way of 54*91f16700Schasingluluboot sequence to support TBBR. 55*91f16700Schasinglulu 56*91f16700SchasingluluBootrom --> SPL --> BL2 --> BL31 --> BL33(u-boot with UEFI) --> grub 57*91f16700Schasinglulu 58*91f16700SchasingluluThis helps us to fulfill the SystemReady EBBR standard. 59*91f16700SchasingluluBL2 will be in the FIT image and SPL will verify it. 60*91f16700SchasingluluAll of the BL3x will be put in the FIP image. BL2 will verify them. 61*91f16700SchasingluluIn U-boot we turn on the UEFI secure boot features so it can verify 62*91f16700Schasinglulugrub. And we use grub to verify linux kernel. 63*91f16700Schasinglulu 64*91f16700SchasingluluMeasured Boot 65*91f16700Schasinglulu------------- 66*91f16700Schasinglulu 67*91f16700SchasingluluWhen setting MEASURED_BOOT=1 on imx8mm we can let TF-A generate event logs 68*91f16700Schasingluluwith a DTB overlay. The overlay will be put at PLAT_IMX8M_DTO_BASE with 69*91f16700Schasinglulumaximum size PLAT_IMX8M_DTO_MAX_SIZE. Then in U-boot we can apply the DTB 70*91f16700Schasingluluoverlay and let U-boot to parse the event log and update the PCRs. 71*91f16700Schasinglulu 72*91f16700SchasingluluHigh Assurance Boot (HABv4) 73*91f16700Schasinglulu--------------------------- 74*91f16700Schasinglulu 75*91f16700SchasingluluAll actively maintained platforms have a support for High Assurance 76*91f16700SchasingluluBoot (HABv4), which is implemented via ROM Vector Table (RVT) API to 77*91f16700Schasingluluextend the Root-of-Trust beyond the SPL. Those calls are done via SMC 78*91f16700Schasingluluand are executed in EL3, with results returned back to original caller. 79*91f16700Schasinglulu 80*91f16700SchasingluluNote on DRAM Memory Mapping 81*91f16700Schasinglulu~~~~~~~~~~~~~~~~~~~~~~~~~~~ 82*91f16700Schasinglulu 83*91f16700SchasingluluThere is a special case of mapping the DRAM: entire DRAM available on the 84*91f16700Schasingluluplatform is mapped into the EL3 with MT_RW attributes. 85*91f16700Schasinglulu 86*91f16700SchasingluluMapping the entire DRAM allows the usage of 2MB block mapping in Level-2 87*91f16700SchasingluluTranslation Table entries, which use less Page Table Entries (PTEs). If 88*91f16700SchasingluluLevel-3 PTE mapping is used instead then additional PTEs would be required, 89*91f16700Schasingluluwhich leads to the increase of translation table size. 90*91f16700Schasinglulu 91*91f16700SchasingluluDue to the fact that the size of SRAM is limited on some platforms in the 92*91f16700Schasinglulufamily it should rather be avoided creating additional Level-3 mapping and 93*91f16700Schasingluluintroduce more PTEs, hence the implementation uses Level-2 mapping which 94*91f16700Schasinglulumaps entire DRAM space. 95*91f16700Schasinglulu 96*91f16700SchasingluluThe reason for the MT_RW attribute mapping scheme is the fact that the SMC 97*91f16700SchasingluluAPI to get the status and events is called from NS world passing destination 98*91f16700Schasinglulupointers which are located in DRAM. Mapping DRAM without MT_RW permissions 99*91f16700Schasinglulucauses those locations not to be filled, which in turn causing EL1&0 software 100*91f16700Schasinglulunot to receive replies. 101*91f16700Schasinglulu 102*91f16700SchasingluluTherefore, DRAM mapping is done with MT_RW attributes, as it is required for 103*91f16700Schasingluludata exchange between EL3 and EL1&0 software. 104*91f16700Schasinglulu 105*91f16700SchasingluluReference Documentation 106*91f16700Schasinglulu~~~~~~~~~~~~~~~~~~~~~~~ 107*91f16700Schasinglulu 108*91f16700SchasingluluDetails on HABv4 usage and implementation could be found in following documents: 109*91f16700Schasinglulu 110*91f16700Schasinglulu- AN4581: "i.MX Secure Boot on HABv4 Supported Devices", Rev. 4 - June 2020 111*91f16700Schasinglulu- AN12263: "HABv4 RVT Guidelines and Recommendations", Rev. 1 - 06/2020 112*91f16700Schasinglulu- "HABv4 API Reference Manual". This document in the part of NXP Code Signing Tool (CST) distribution. 113*91f16700Schasinglulu 114