1*91f16700SchasingluluTC Total Compute Platform 2*91f16700Schasinglulu========================== 3*91f16700Schasinglulu 4*91f16700SchasingluluSome of the features of TC platform referenced in TF-A include: 5*91f16700Schasinglulu 6*91f16700Schasinglulu- A `System Control Processor <https://github.com/ARM-software/SCP-firmware>`_ 7*91f16700Schasinglulu to abstract power and system management tasks away from application 8*91f16700Schasinglulu processors. The RAM firmware for SCP is included in the TF-A FIP and is 9*91f16700Schasinglulu loaded by AP BL2 from FIP in flash to SRAM for copying by SCP (SCP has access 10*91f16700Schasinglulu to AP SRAM). 11*91f16700Schasinglulu- GICv4 12*91f16700Schasinglulu- Trusted Board Boot 13*91f16700Schasinglulu- SCMI 14*91f16700Schasinglulu- MHUv2 15*91f16700Schasinglulu 16*91f16700SchasingluluCurrently, the main difference between TC0 (TARGET_PLATFORM=0), TC1 17*91f16700Schasinglulu(TARGET_PLATFORM=1), TC2 (TARGET_PLATFORM=2) platforms w.r.t to TF-A 18*91f16700Schasingluluis the CPUs supported as below: 19*91f16700Schasinglulu 20*91f16700Schasinglulu- TC0 has support for Cortex A510, Cortex A710 and Cortex X2. (Note TC0 is now deprecated) 21*91f16700Schasinglulu- TC1 has support for Cortex A510, Cortex A715 and Cortex X3. (Note TC1 is now deprecated) 22*91f16700Schasinglulu- TC2 has support for Cortex A520, Cortex A720 and Cortex x4. 23*91f16700Schasinglulu 24*91f16700SchasingluluBoot Sequence 25*91f16700Schasinglulu------------- 26*91f16700Schasinglulu 27*91f16700SchasingluluThe execution begins from SCP_BL1. SCP_BL1 powers up the AP which starts 28*91f16700Schasingluluexecuting AP_BL1 and then executes AP_BL2 which loads the SCP_BL2 from 29*91f16700SchasingluluFIP to SRAM. The SCP has access to AP SRAM. The address and size of SCP_BL2 30*91f16700Schasingluluis communicated to SCP using SDS. SCP copies SCP_BL2 from SRAM to its own 31*91f16700SchasingluluRAM and starts executing it. The AP then continues executing the rest of TF-A 32*91f16700Schasinglulustages including BL31 runtime stage and hands off executing to 33*91f16700SchasingluluNon-secure world (u-boot). 34*91f16700Schasinglulu 35*91f16700SchasingluluBuild Procedure (TF-A only) 36*91f16700Schasinglulu~~~~~~~~~~~~~~~~~~~~~~~~~~~ 37*91f16700Schasinglulu 38*91f16700Schasinglulu- Obtain `Arm toolchain`_ and set the CROSS_COMPILE environment variable to 39*91f16700Schasinglulu point to the toolchain folder. 40*91f16700Schasinglulu 41*91f16700Schasinglulu- Build TF-A: 42*91f16700Schasinglulu 43*91f16700Schasinglulu .. code:: shell 44*91f16700Schasinglulu 45*91f16700Schasinglulu make PLAT=tc BL33=<path_to_uboot.bin> \ 46*91f16700Schasinglulu SCP_BL2=<path_to_scp_ramfw.bin> TARGET_PLATFORM={0,1,2} all fip 47*91f16700Schasinglulu 48*91f16700Schasinglulu Enable TBBR by adding the following options to the make command: 49*91f16700Schasinglulu 50*91f16700Schasinglulu .. code:: shell 51*91f16700Schasinglulu 52*91f16700Schasinglulu MBEDTLS_DIR=<path_to_mbedtls_directory> \ 53*91f16700Schasinglulu TRUSTED_BOARD_BOOT=1 \ 54*91f16700Schasinglulu GENERATE_COT=1 \ 55*91f16700Schasinglulu ARM_ROTPK_LOCATION=devel_rsa \ 56*91f16700Schasinglulu ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem 57*91f16700Schasinglulu 58*91f16700Schasinglulu-------------- 59*91f16700Schasinglulu 60*91f16700Schasinglulu*Copyright (c) 2020-2023, Arm Limited. All rights reserved.* 61*91f16700Schasinglulu 62*91f16700Schasinglulu.. _Arm Toolchain: https://developer.arm.com/tools-and-software/open-source-software/developer-tools/gnu-toolchain/downloads 63