1*91f16700SchasingluluMaximum Power Mitigation Mechanism (MPMM) Bindings 2*91f16700Schasinglulu================================================== 3*91f16700Schasinglulu 4*91f16700Schasinglulu|MPMM| support cannot be determined at runtime by the firmware. Instead, these 5*91f16700SchasingluluDTB bindings allow the platform to communicate per-core support for |MPMM| via 6*91f16700Schasingluluthe ``HW_CONFIG`` device tree blob. 7*91f16700Schasinglulu 8*91f16700SchasingluluBindings 9*91f16700Schasinglulu^^^^^^^^ 10*91f16700Schasinglulu 11*91f16700Schasinglulu.. contents:: 12*91f16700Schasinglulu :local: 13*91f16700Schasinglulu 14*91f16700Schasinglulu``/cpus/cpus/cpu*`` node properties 15*91f16700Schasinglulu""""""""""""""""""""""""""""""""""" 16*91f16700Schasinglulu 17*91f16700SchasingluluThe ``cpu`` node has been augmented to allow the platform to indicate support 18*91f16700Schasinglulufor |MPMM| on a given core. 19*91f16700Schasinglulu 20*91f16700Schasinglulu+-------------------+-------+-------------+------------------------------------+ 21*91f16700Schasinglulu| Property name | Usage | Value type | Description | 22*91f16700Schasinglulu+===================+=======+=============+====================================+ 23*91f16700Schasinglulu| ``supports-mpmm`` | O | ``<empty>`` | If present, indicates that |MPMM| | 24*91f16700Schasinglulu| | | | is available on this core. | 25*91f16700Schasinglulu+-------------------+-------+-------------+------------------------------------+ 26*91f16700Schasinglulu 27*91f16700SchasingluluExample 28*91f16700Schasinglulu^^^^^^^ 29*91f16700Schasinglulu 30*91f16700SchasingluluAn example system offering two cores, one with support for |MPMM| and one 31*91f16700Schasingluluwithout, can be described as follows: 32*91f16700Schasinglulu 33*91f16700Schasinglulu.. code-block:: 34*91f16700Schasinglulu 35*91f16700Schasinglulu cpus { 36*91f16700Schasinglulu #address-cells = <2>; 37*91f16700Schasinglulu #size-cells = <0>; 38*91f16700Schasinglulu 39*91f16700Schasinglulu cpu0@00000 { 40*91f16700Schasinglulu ... 41*91f16700Schasinglulu 42*91f16700Schasinglulu supports-mpmm; 43*91f16700Schasinglulu }; 44*91f16700Schasinglulu 45*91f16700Schasinglulu cpu1@00100 { 46*91f16700Schasinglulu ... 47*91f16700Schasinglulu }; 48*91f16700Schasinglulu } 49