1*91f16700Schasinglulu/* 2*91f16700Schasinglulu * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu#include <arch.h> 8*91f16700Schasinglulu#include <asm_macros.S> 9*91f16700Schasinglulu#include <bl32/tsp/tsp.h> 10*91f16700Schasinglulu#include <common/bl_common.h> 11*91f16700Schasinglulu 12*91f16700Schasinglulu /* ---------------------------------------------------- 13*91f16700Schasinglulu * The caller-saved registers x0-x18 and LR are saved 14*91f16700Schasinglulu * here. 15*91f16700Schasinglulu * ---------------------------------------------------- 16*91f16700Schasinglulu */ 17*91f16700Schasinglulu 18*91f16700Schasinglulu#define SCRATCH_REG_SIZE #(20 * 8) 19*91f16700Schasinglulu 20*91f16700Schasinglulu .macro save_caller_regs_and_lr 21*91f16700Schasinglulu sub sp, sp, SCRATCH_REG_SIZE 22*91f16700Schasinglulu stp x0, x1, [sp] 23*91f16700Schasinglulu stp x2, x3, [sp, #0x10] 24*91f16700Schasinglulu stp x4, x5, [sp, #0x20] 25*91f16700Schasinglulu stp x6, x7, [sp, #0x30] 26*91f16700Schasinglulu stp x8, x9, [sp, #0x40] 27*91f16700Schasinglulu stp x10, x11, [sp, #0x50] 28*91f16700Schasinglulu stp x12, x13, [sp, #0x60] 29*91f16700Schasinglulu stp x14, x15, [sp, #0x70] 30*91f16700Schasinglulu stp x16, x17, [sp, #0x80] 31*91f16700Schasinglulu stp x18, x30, [sp, #0x90] 32*91f16700Schasinglulu .endm 33*91f16700Schasinglulu 34*91f16700Schasinglulu .macro restore_caller_regs_and_lr 35*91f16700Schasinglulu ldp x0, x1, [sp] 36*91f16700Schasinglulu ldp x2, x3, [sp, #0x10] 37*91f16700Schasinglulu ldp x4, x5, [sp, #0x20] 38*91f16700Schasinglulu ldp x6, x7, [sp, #0x30] 39*91f16700Schasinglulu ldp x8, x9, [sp, #0x40] 40*91f16700Schasinglulu ldp x10, x11, [sp, #0x50] 41*91f16700Schasinglulu ldp x12, x13, [sp, #0x60] 42*91f16700Schasinglulu ldp x14, x15, [sp, #0x70] 43*91f16700Schasinglulu ldp x16, x17, [sp, #0x80] 44*91f16700Schasinglulu ldp x18, x30, [sp, #0x90] 45*91f16700Schasinglulu add sp, sp, SCRATCH_REG_SIZE 46*91f16700Schasinglulu .endm 47*91f16700Schasinglulu 48*91f16700Schasinglulu /* ---------------------------------------------------- 49*91f16700Schasinglulu * Common TSP interrupt handling routine 50*91f16700Schasinglulu * ---------------------------------------------------- 51*91f16700Schasinglulu */ 52*91f16700Schasinglulu .macro handle_tsp_interrupt label 53*91f16700Schasinglulu /* Enable the SError interrupt */ 54*91f16700Schasinglulu msr daifclr, #DAIF_ABT_BIT 55*91f16700Schasinglulu 56*91f16700Schasinglulu save_caller_regs_and_lr 57*91f16700Schasinglulu bl tsp_common_int_handler 58*91f16700Schasinglulu cbz x0, interrupt_exit_\label 59*91f16700Schasinglulu 60*91f16700Schasinglulu /* 61*91f16700Schasinglulu * This interrupt was not targetted to S-EL1 so send it to 62*91f16700Schasinglulu * the monitor and wait for execution to resume. 63*91f16700Schasinglulu */ 64*91f16700Schasinglulu smc #0 65*91f16700Schasingluluinterrupt_exit_\label: 66*91f16700Schasinglulu restore_caller_regs_and_lr 67*91f16700Schasinglulu exception_return 68*91f16700Schasinglulu .endm 69*91f16700Schasinglulu 70*91f16700Schasinglulu .globl tsp_exceptions 71*91f16700Schasinglulu 72*91f16700Schasinglulu /* ----------------------------------------------------- 73*91f16700Schasinglulu * TSP exception handlers. 74*91f16700Schasinglulu * ----------------------------------------------------- 75*91f16700Schasinglulu */ 76*91f16700Schasingluluvector_base tsp_exceptions 77*91f16700Schasinglulu /* ----------------------------------------------------- 78*91f16700Schasinglulu * Current EL with _sp_el0 : 0x0 - 0x200. No exceptions 79*91f16700Schasinglulu * are expected and treated as irrecoverable errors. 80*91f16700Schasinglulu * ----------------------------------------------------- 81*91f16700Schasinglulu */ 82*91f16700Schasingluluvector_entry sync_exception_sp_el0 83*91f16700Schasinglulu b plat_panic_handler 84*91f16700Schasingluluend_vector_entry sync_exception_sp_el0 85*91f16700Schasinglulu 86*91f16700Schasingluluvector_entry irq_sp_el0 87*91f16700Schasinglulu b plat_panic_handler 88*91f16700Schasingluluend_vector_entry irq_sp_el0 89*91f16700Schasinglulu 90*91f16700Schasingluluvector_entry fiq_sp_el0 91*91f16700Schasinglulu b plat_panic_handler 92*91f16700Schasingluluend_vector_entry fiq_sp_el0 93*91f16700Schasinglulu 94*91f16700Schasingluluvector_entry serror_sp_el0 95*91f16700Schasinglulu b plat_panic_handler 96*91f16700Schasingluluend_vector_entry serror_sp_el0 97*91f16700Schasinglulu 98*91f16700Schasinglulu 99*91f16700Schasinglulu /* ----------------------------------------------------- 100*91f16700Schasinglulu * Current EL with SPx: 0x200 - 0x400. Only IRQs/FIQs 101*91f16700Schasinglulu * are expected and handled 102*91f16700Schasinglulu * ----------------------------------------------------- 103*91f16700Schasinglulu */ 104*91f16700Schasingluluvector_entry sync_exception_sp_elx 105*91f16700Schasinglulu b plat_panic_handler 106*91f16700Schasingluluend_vector_entry sync_exception_sp_elx 107*91f16700Schasinglulu 108*91f16700Schasingluluvector_entry irq_sp_elx 109*91f16700Schasinglulu handle_tsp_interrupt irq_sp_elx 110*91f16700Schasingluluend_vector_entry irq_sp_elx 111*91f16700Schasinglulu 112*91f16700Schasingluluvector_entry fiq_sp_elx 113*91f16700Schasinglulu handle_tsp_interrupt fiq_sp_elx 114*91f16700Schasingluluend_vector_entry fiq_sp_elx 115*91f16700Schasinglulu 116*91f16700Schasingluluvector_entry serror_sp_elx 117*91f16700Schasinglulu b plat_panic_handler 118*91f16700Schasingluluend_vector_entry serror_sp_elx 119*91f16700Schasinglulu 120*91f16700Schasinglulu 121*91f16700Schasinglulu /* ----------------------------------------------------- 122*91f16700Schasinglulu * Lower EL using AArch64 : 0x400 - 0x600. No exceptions 123*91f16700Schasinglulu * are handled since TSP does not implement a lower EL 124*91f16700Schasinglulu * ----------------------------------------------------- 125*91f16700Schasinglulu */ 126*91f16700Schasingluluvector_entry sync_exception_aarch64 127*91f16700Schasinglulu b plat_panic_handler 128*91f16700Schasingluluend_vector_entry sync_exception_aarch64 129*91f16700Schasinglulu 130*91f16700Schasingluluvector_entry irq_aarch64 131*91f16700Schasinglulu b plat_panic_handler 132*91f16700Schasingluluend_vector_entry irq_aarch64 133*91f16700Schasinglulu 134*91f16700Schasingluluvector_entry fiq_aarch64 135*91f16700Schasinglulu b plat_panic_handler 136*91f16700Schasingluluend_vector_entry fiq_aarch64 137*91f16700Schasinglulu 138*91f16700Schasingluluvector_entry serror_aarch64 139*91f16700Schasinglulu b plat_panic_handler 140*91f16700Schasingluluend_vector_entry serror_aarch64 141*91f16700Schasinglulu 142*91f16700Schasinglulu 143*91f16700Schasinglulu /* ----------------------------------------------------- 144*91f16700Schasinglulu * Lower EL using AArch32 : 0x600 - 0x800. No exceptions 145*91f16700Schasinglulu * handled since the TSP does not implement a lower EL. 146*91f16700Schasinglulu * ----------------------------------------------------- 147*91f16700Schasinglulu */ 148*91f16700Schasingluluvector_entry sync_exception_aarch32 149*91f16700Schasinglulu b plat_panic_handler 150*91f16700Schasingluluend_vector_entry sync_exception_aarch32 151*91f16700Schasinglulu 152*91f16700Schasingluluvector_entry irq_aarch32 153*91f16700Schasinglulu b plat_panic_handler 154*91f16700Schasingluluend_vector_entry irq_aarch32 155*91f16700Schasinglulu 156*91f16700Schasingluluvector_entry fiq_aarch32 157*91f16700Schasinglulu b plat_panic_handler 158*91f16700Schasingluluend_vector_entry fiq_aarch32 159*91f16700Schasinglulu 160*91f16700Schasingluluvector_entry serror_aarch32 161*91f16700Schasinglulu b plat_panic_handler 162*91f16700Schasingluluend_vector_entry serror_aarch32 163