1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2022, ARM Limited. All rights reserved. 3*91f16700Schasinglulu * Copyright (c) 2023, NVIDIA Corporation. All rights reserved. 4*91f16700Schasinglulu * 5*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 6*91f16700Schasinglulu * 7*91f16700Schasinglulu * Dispatch synchronous system register traps from lower ELs. 8*91f16700Schasinglulu */ 9*91f16700Schasinglulu 10*91f16700Schasinglulu #include <bl31/sync_handle.h> 11*91f16700Schasinglulu #include <context.h> 12*91f16700Schasinglulu 13*91f16700Schasinglulu int handle_sysreg_trap(uint64_t esr_el3, cpu_context_t *ctx) 14*91f16700Schasinglulu { 15*91f16700Schasinglulu uint64_t __unused opcode = esr_el3 & ISS_SYSREG_OPCODE_MASK; 16*91f16700Schasinglulu 17*91f16700Schasinglulu #if ENABLE_FEAT_RNG_TRAP 18*91f16700Schasinglulu if ((opcode == ISS_SYSREG_OPCODE_RNDR) || (opcode == ISS_SYSREG_OPCODE_RNDRRS)) { 19*91f16700Schasinglulu return plat_handle_rng_trap(esr_el3, ctx); 20*91f16700Schasinglulu } 21*91f16700Schasinglulu #endif 22*91f16700Schasinglulu 23*91f16700Schasinglulu #if IMPDEF_SYSREG_TRAP 24*91f16700Schasinglulu if ((opcode & ISS_SYSREG_OPCODE_IMPDEF) == ISS_SYSREG_OPCODE_IMPDEF) { 25*91f16700Schasinglulu return plat_handle_impdef_trap(esr_el3, ctx); 26*91f16700Schasinglulu } 27*91f16700Schasinglulu #endif 28*91f16700Schasinglulu 29*91f16700Schasinglulu return TRAP_RET_UNHANDLED; 30*91f16700Schasinglulu } 31