1*91f16700Schasinglulu/* 2*91f16700Schasinglulu * Copyright (c) 2016-2022, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu#include <arch.h> 8*91f16700Schasinglulu#include <asm_macros.S> 9*91f16700Schasinglulu#include <common/bl_common.h> 10*91f16700Schasinglulu 11*91f16700Schasinglulu .globl bl2u_vector_table 12*91f16700Schasinglulu .globl bl2u_entrypoint 13*91f16700Schasinglulu 14*91f16700Schasinglulu 15*91f16700Schasingluluvector_base bl2u_vector_table 16*91f16700Schasinglulu b bl2u_entrypoint 17*91f16700Schasinglulu b report_exception /* Undef */ 18*91f16700Schasinglulu b report_exception /* SVC call */ 19*91f16700Schasinglulu b report_prefetch_abort /* Prefetch abort */ 20*91f16700Schasinglulu b report_data_abort /* Data abort */ 21*91f16700Schasinglulu b report_exception /* Reserved */ 22*91f16700Schasinglulu b report_exception /* IRQ */ 23*91f16700Schasinglulu b report_exception /* FIQ */ 24*91f16700Schasinglulu 25*91f16700Schasinglulu 26*91f16700Schasinglulufunc bl2u_entrypoint 27*91f16700Schasinglulu /*--------------------------------------------- 28*91f16700Schasinglulu * Save from r1 the extents of the trusted ram 29*91f16700Schasinglulu * available to BL2U for future use. 30*91f16700Schasinglulu * r0 is not currently used. 31*91f16700Schasinglulu * --------------------------------------------- 32*91f16700Schasinglulu */ 33*91f16700Schasinglulu mov r11, r1 34*91f16700Schasinglulu mov r10, r2 35*91f16700Schasinglulu 36*91f16700Schasinglulu /* --------------------------------------------- 37*91f16700Schasinglulu * Set the exception vector to something sane. 38*91f16700Schasinglulu * --------------------------------------------- 39*91f16700Schasinglulu */ 40*91f16700Schasinglulu ldr r0, =bl2u_vector_table 41*91f16700Schasinglulu stcopr r0, VBAR 42*91f16700Schasinglulu isb 43*91f16700Schasinglulu 44*91f16700Schasinglulu /* -------------------------------------------------------- 45*91f16700Schasinglulu * Enable the instruction cache - disable speculative loads 46*91f16700Schasinglulu * -------------------------------------------------------- 47*91f16700Schasinglulu */ 48*91f16700Schasinglulu ldcopr r0, SCTLR 49*91f16700Schasinglulu orr r0, r0, #SCTLR_I_BIT 50*91f16700Schasinglulu bic r0, r0, #SCTLR_DSSBS_BIT 51*91f16700Schasinglulu stcopr r0, SCTLR 52*91f16700Schasinglulu isb 53*91f16700Schasinglulu 54*91f16700Schasinglulu /* --------------------------------------------- 55*91f16700Schasinglulu * Since BL2U executes after BL1, it is assumed 56*91f16700Schasinglulu * here that BL1 has already has done the 57*91f16700Schasinglulu * necessary register initializations. 58*91f16700Schasinglulu * --------------------------------------------- 59*91f16700Schasinglulu */ 60*91f16700Schasinglulu 61*91f16700Schasinglulu /* --------------------------------------------- 62*91f16700Schasinglulu * Invalidate the RW memory used by the BL2U 63*91f16700Schasinglulu * image. This includes the data and NOBITS 64*91f16700Schasinglulu * sections. This is done to safeguard against 65*91f16700Schasinglulu * possible corruption of this memory by dirty 66*91f16700Schasinglulu * cache lines in a system cache as a result of 67*91f16700Schasinglulu * use by an earlier boot loader stage. 68*91f16700Schasinglulu * --------------------------------------------- 69*91f16700Schasinglulu */ 70*91f16700Schasinglulu ldr r0, =__RW_START__ 71*91f16700Schasinglulu ldr r1, =__RW_END__ 72*91f16700Schasinglulu sub r1, r1, r0 73*91f16700Schasinglulu bl inv_dcache_range 74*91f16700Schasinglulu 75*91f16700Schasinglulu /* --------------------------------------------- 76*91f16700Schasinglulu * Zero out NOBITS sections. There are 2 of them: 77*91f16700Schasinglulu * - the .bss section; 78*91f16700Schasinglulu * - the coherent memory section. 79*91f16700Schasinglulu * --------------------------------------------- 80*91f16700Schasinglulu */ 81*91f16700Schasinglulu ldr r0, =__BSS_START__ 82*91f16700Schasinglulu ldr r1, =__BSS_END__ 83*91f16700Schasinglulu sub r1, r1, r0 84*91f16700Schasinglulu bl zeromem 85*91f16700Schasinglulu 86*91f16700Schasinglulu /* -------------------------------------------- 87*91f16700Schasinglulu * Allocate a stack whose memory will be marked 88*91f16700Schasinglulu * as Normal-IS-WBWA when the MMU is enabled. 89*91f16700Schasinglulu * There is no risk of reading stale stack 90*91f16700Schasinglulu * memory after enabling the MMU as only the 91*91f16700Schasinglulu * primary cpu is running at the moment. 92*91f16700Schasinglulu * -------------------------------------------- 93*91f16700Schasinglulu */ 94*91f16700Schasinglulu bl plat_set_my_stack 95*91f16700Schasinglulu 96*91f16700Schasinglulu /* --------------------------------------------- 97*91f16700Schasinglulu * Initialize the stack protector canary before 98*91f16700Schasinglulu * any C code is called. 99*91f16700Schasinglulu * --------------------------------------------- 100*91f16700Schasinglulu */ 101*91f16700Schasinglulu#if STACK_PROTECTOR_ENABLED 102*91f16700Schasinglulu bl update_stack_protector_canary 103*91f16700Schasinglulu#endif 104*91f16700Schasinglulu 105*91f16700Schasinglulu /* --------------------------------------------- 106*91f16700Schasinglulu * Perform early platform setup & platform 107*91f16700Schasinglulu * specific early arch. setup e.g. mmu setup 108*91f16700Schasinglulu * --------------------------------------------- 109*91f16700Schasinglulu */ 110*91f16700Schasinglulu mov r0, r11 111*91f16700Schasinglulu mov r1, r10 112*91f16700Schasinglulu bl bl2u_early_platform_setup 113*91f16700Schasinglulu bl bl2u_plat_arch_setup 114*91f16700Schasinglulu 115*91f16700Schasinglulu /* --------------------------------------------- 116*91f16700Schasinglulu * Jump to main function. 117*91f16700Schasinglulu * --------------------------------------------- 118*91f16700Schasinglulu */ 119*91f16700Schasinglulu bl bl2u_main 120*91f16700Schasinglulu 121*91f16700Schasinglulu /* --------------------------------------------- 122*91f16700Schasinglulu * Should never reach this point. 123*91f16700Schasinglulu * --------------------------------------------- 124*91f16700Schasinglulu */ 125*91f16700Schasinglulu no_ret plat_panic_handler 126*91f16700Schasinglulu 127*91f16700Schasingluluendfunc bl2u_entrypoint 128