1*91f16700Schasinglulu/* 2*91f16700Schasinglulu * Copyright (c) 2021, Arm Limited. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu#include <arch.h> 8*91f16700Schasinglulu#include <asm_macros.S> 9*91f16700Schasinglulu#include <common/bl_common.h> 10*91f16700Schasinglulu 11*91f16700Schasinglulu .globl bl2_run_next_image 12*91f16700Schasinglulu 13*91f16700Schasinglulu 14*91f16700Schasinglulufunc bl2_run_next_image 15*91f16700Schasinglulu mov x20,x0 16*91f16700Schasinglulu /* --------------------------------------------- 17*91f16700Schasinglulu * MMU needs to be disabled because both BL2 and BL31 execute 18*91f16700Schasinglulu * in EL3, and therefore share the same address space. 19*91f16700Schasinglulu * BL31 will initialize the address space according to its 20*91f16700Schasinglulu * own requirement. 21*91f16700Schasinglulu * --------------------------------------------- 22*91f16700Schasinglulu */ 23*91f16700Schasinglulu bl disable_mmu_icache_el3 24*91f16700Schasinglulu tlbi alle3 25*91f16700Schasinglulu bl bl2_el3_plat_prepare_exit 26*91f16700Schasinglulu 27*91f16700Schasinglulu ldp x0, x1, [x20, #ENTRY_POINT_INFO_PC_OFFSET] 28*91f16700Schasinglulu msr elr_el3, x0 29*91f16700Schasinglulu msr spsr_el3, x1 30*91f16700Schasinglulu 31*91f16700Schasinglulu ldp x6, x7, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x30)] 32*91f16700Schasinglulu ldp x4, x5, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x20)] 33*91f16700Schasinglulu ldp x2, x3, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x10)] 34*91f16700Schasinglulu ldp x0, x1, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x0)] 35*91f16700Schasinglulu exception_return 36*91f16700Schasingluluendfunc bl2_run_next_image 37