xref: /arm-trusted-firmware/bl2/aarch32/bl2_run_next_image.S (revision 91f16700b400a8c0651d24a598fc48ee2997a0d7)
1*91f16700Schasinglulu/*
2*91f16700Schasinglulu * Copyright (c) 2021, Arm Limited. All rights reserved.
3*91f16700Schasinglulu *
4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause
5*91f16700Schasinglulu */
6*91f16700Schasinglulu
7*91f16700Schasinglulu#include <arch.h>
8*91f16700Schasinglulu#include <asm_macros.S>
9*91f16700Schasinglulu#include <common/bl_common.h>
10*91f16700Schasinglulu
11*91f16700Schasinglulu	.globl	bl2_run_next_image
12*91f16700Schasinglulu
13*91f16700Schasinglulu
14*91f16700Schasinglulufunc bl2_run_next_image
15*91f16700Schasinglulu	mov	r8,r0
16*91f16700Schasinglulu
17*91f16700Schasinglulu	/*
18*91f16700Schasinglulu	 * MMU needs to be disabled because both BL2 and BL32 execute
19*91f16700Schasinglulu	 * in PL1, and therefore share the same address space.
20*91f16700Schasinglulu	 * BL32 will initialize the address space according to its
21*91f16700Schasinglulu	 * own requirement.
22*91f16700Schasinglulu	 */
23*91f16700Schasinglulu	bl	disable_mmu_icache_secure
24*91f16700Schasinglulu	stcopr	r0, TLBIALL
25*91f16700Schasinglulu	dsb	sy
26*91f16700Schasinglulu	isb
27*91f16700Schasinglulu	mov	r0, r8
28*91f16700Schasinglulu	bl	bl2_el3_plat_prepare_exit
29*91f16700Schasinglulu
30*91f16700Schasinglulu	/*
31*91f16700Schasinglulu	 * Extract PC and SPSR based on struct `entry_point_info_t`
32*91f16700Schasinglulu	 * and load it in LR and SPSR registers respectively.
33*91f16700Schasinglulu	 */
34*91f16700Schasinglulu	ldr	lr, [r8, #ENTRY_POINT_INFO_PC_OFFSET]
35*91f16700Schasinglulu	ldr	r1, [r8, #(ENTRY_POINT_INFO_PC_OFFSET + 4)]
36*91f16700Schasinglulu	msr	spsr_xc, r1
37*91f16700Schasinglulu
38*91f16700Schasinglulu	/* Some BL32 stages expect lr_svc to provide the BL33 entry address */
39*91f16700Schasinglulu	cps	#MODE32_svc
40*91f16700Schasinglulu	ldr	lr, [r8, #ENTRY_POINT_INFO_LR_SVC_OFFSET]
41*91f16700Schasinglulu	cps	#MODE32_mon
42*91f16700Schasinglulu
43*91f16700Schasinglulu	add	r8, r8, #ENTRY_POINT_INFO_ARGS_OFFSET
44*91f16700Schasinglulu	ldm	r8, {r0, r1, r2, r3}
45*91f16700Schasinglulu	exception_return
46*91f16700Schasingluluendfunc bl2_run_next_image
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