1*91f16700Schasinglulu/* 2*91f16700Schasinglulu * Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu#include <arch.h> 8*91f16700Schasinglulu#include <asm_macros.S> 9*91f16700Schasinglulu#include <common/bl_common.h> 10*91f16700Schasinglulu 11*91f16700Schasinglulu .globl bl2_vector_table 12*91f16700Schasinglulu 13*91f16700Schasingluluvector_base bl2_vector_table 14*91f16700Schasinglulu b bl2_entrypoint 15*91f16700Schasinglulu b report_exception /* Undef */ 16*91f16700Schasinglulu b report_exception /* SVC call */ 17*91f16700Schasinglulu b report_prefetch_abort /* Prefetch abort */ 18*91f16700Schasinglulu b report_data_abort /* Data abort */ 19*91f16700Schasinglulu b report_exception /* Reserved */ 20*91f16700Schasinglulu b report_exception /* IRQ */ 21*91f16700Schasinglulu b report_exception /* FIQ */ 22