1*91f16700Schasinglulu/* 2*91f16700Schasinglulu * Copyright (c) 2013-2021, Arm Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu#include <arch.h> 8*91f16700Schasinglulu#include <common/bl_common.h> 9*91f16700Schasinglulu#include <el3_common_macros.S> 10*91f16700Schasinglulu 11*91f16700Schasinglulu .globl bl1_entrypoint 12*91f16700Schasinglulu .globl bl1_run_bl2_in_root 13*91f16700Schasinglulu 14*91f16700Schasinglulu 15*91f16700Schasinglulu /* ----------------------------------------------------- 16*91f16700Schasinglulu * bl1_entrypoint() is the entry point into the trusted 17*91f16700Schasinglulu * firmware code when a cpu is released from warm or 18*91f16700Schasinglulu * cold reset. 19*91f16700Schasinglulu * ----------------------------------------------------- 20*91f16700Schasinglulu */ 21*91f16700Schasinglulu 22*91f16700Schasinglulufunc bl1_entrypoint 23*91f16700Schasinglulu /* --------------------------------------------------------------------- 24*91f16700Schasinglulu * If the reset address is programmable then bl1_entrypoint() is 25*91f16700Schasinglulu * executed only on the cold boot path. Therefore, we can skip the warm 26*91f16700Schasinglulu * boot mailbox mechanism. 27*91f16700Schasinglulu * --------------------------------------------------------------------- 28*91f16700Schasinglulu */ 29*91f16700Schasinglulu el3_entrypoint_common \ 30*91f16700Schasinglulu _init_sctlr=1 \ 31*91f16700Schasinglulu _warm_boot_mailbox=!PROGRAMMABLE_RESET_ADDRESS \ 32*91f16700Schasinglulu _secondary_cold_boot=!COLD_BOOT_SINGLE_CPU \ 33*91f16700Schasinglulu _init_memory=1 \ 34*91f16700Schasinglulu _init_c_runtime=1 \ 35*91f16700Schasinglulu _exception_vectors=bl1_exceptions \ 36*91f16700Schasinglulu _pie_fixup_size=0 37*91f16700Schasinglulu 38*91f16700Schasinglulu /* -------------------------------------------------------------------- 39*91f16700Schasinglulu * Perform BL1 setup 40*91f16700Schasinglulu * -------------------------------------------------------------------- 41*91f16700Schasinglulu */ 42*91f16700Schasinglulu bl bl1_setup 43*91f16700Schasinglulu 44*91f16700Schasinglulu#if ENABLE_PAUTH 45*91f16700Schasinglulu /* -------------------------------------------------------------------- 46*91f16700Schasinglulu * Program APIAKey_EL1 and enable pointer authentication. 47*91f16700Schasinglulu * -------------------------------------------------------------------- 48*91f16700Schasinglulu */ 49*91f16700Schasinglulu bl pauth_init_enable_el3 50*91f16700Schasinglulu#endif /* ENABLE_PAUTH */ 51*91f16700Schasinglulu 52*91f16700Schasinglulu /* -------------------------------------------------------------------- 53*91f16700Schasinglulu * Initialize platform and jump to our c-entry point 54*91f16700Schasinglulu * for this type of reset. 55*91f16700Schasinglulu * -------------------------------------------------------------------- 56*91f16700Schasinglulu */ 57*91f16700Schasinglulu bl bl1_main 58*91f16700Schasinglulu 59*91f16700Schasinglulu#if ENABLE_PAUTH 60*91f16700Schasinglulu /* -------------------------------------------------------------------- 61*91f16700Schasinglulu * Disable pointer authentication before jumping to next boot image. 62*91f16700Schasinglulu * -------------------------------------------------------------------- 63*91f16700Schasinglulu */ 64*91f16700Schasinglulu bl pauth_disable_el3 65*91f16700Schasinglulu#endif /* ENABLE_PAUTH */ 66*91f16700Schasinglulu 67*91f16700Schasinglulu /* -------------------------------------------------- 68*91f16700Schasinglulu * Do the transition to next boot image. 69*91f16700Schasinglulu * -------------------------------------------------- 70*91f16700Schasinglulu */ 71*91f16700Schasinglulu#if ENABLE_RME 72*91f16700Schasinglulu b bl1_run_bl2_in_root 73*91f16700Schasinglulu#else 74*91f16700Schasinglulu b el3_exit 75*91f16700Schasinglulu#endif 76*91f16700Schasingluluendfunc bl1_entrypoint 77*91f16700Schasinglulu 78*91f16700Schasinglulu /* ----------------------------------------------------- 79*91f16700Schasinglulu * void bl1_run_bl2_in_root(); 80*91f16700Schasinglulu * This function runs BL2 in root/EL3 when RME is enabled. 81*91f16700Schasinglulu * ----------------------------------------------------- 82*91f16700Schasinglulu */ 83*91f16700Schasinglulu 84*91f16700Schasinglulufunc bl1_run_bl2_in_root 85*91f16700Schasinglulu /* read bl2_ep_info */ 86*91f16700Schasinglulu adrp x20, bl2_ep_info 87*91f16700Schasinglulu add x20, x20, :lo12:bl2_ep_info 88*91f16700Schasinglulu ldr x20, [x20] 89*91f16700Schasinglulu 90*91f16700Schasinglulu /* --------------------------------------------- 91*91f16700Schasinglulu * MMU needs to be disabled because BL2 executes 92*91f16700Schasinglulu * in EL3. It will initialize the address space 93*91f16700Schasinglulu * according to its own requirements. 94*91f16700Schasinglulu * --------------------------------------------- 95*91f16700Schasinglulu */ 96*91f16700Schasinglulu bl disable_mmu_icache_el3 97*91f16700Schasinglulu tlbi alle3 98*91f16700Schasinglulu 99*91f16700Schasinglulu ldp x0, x1, [x20, #ENTRY_POINT_INFO_PC_OFFSET] 100*91f16700Schasinglulu msr elr_el3, x0 101*91f16700Schasinglulu msr spsr_el3, x1 102*91f16700Schasinglulu 103*91f16700Schasinglulu ldp x6, x7, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x30)] 104*91f16700Schasinglulu ldp x4, x5, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x20)] 105*91f16700Schasinglulu ldp x2, x3, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x10)] 106*91f16700Schasinglulu ldp x0, x1, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x0)] 107*91f16700Schasinglulu exception_return 108*91f16700Schasingluluendfunc bl1_run_bl2_in_root 109