1*91f16700Schasinglulu/* 2*91f16700Schasinglulu * Copyright (c) 2016-2022, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu#include <arch.h> 8*91f16700Schasinglulu#include <asm_macros.S> 9*91f16700Schasinglulu#include <common/bl_common.h> 10*91f16700Schasinglulu#include <context.h> 11*91f16700Schasinglulu#include <el3_common_macros.S> 12*91f16700Schasinglulu#include <smccc_helpers.h> 13*91f16700Schasinglulu#include <smccc_macros.S> 14*91f16700Schasinglulu 15*91f16700Schasinglulu .globl bl1_vector_table 16*91f16700Schasinglulu .globl bl1_entrypoint 17*91f16700Schasinglulu 18*91f16700Schasinglulu /* ----------------------------------------------------- 19*91f16700Schasinglulu * Setup the vector table to support SVC & MON mode. 20*91f16700Schasinglulu * ----------------------------------------------------- 21*91f16700Schasinglulu */ 22*91f16700Schasingluluvector_base bl1_vector_table 23*91f16700Schasinglulu b bl1_entrypoint 24*91f16700Schasinglulu b report_exception /* Undef */ 25*91f16700Schasinglulu b bl1_aarch32_smc_handler /* SMC call */ 26*91f16700Schasinglulu b report_prefetch_abort /* Prefetch abort */ 27*91f16700Schasinglulu b report_data_abort /* Data abort */ 28*91f16700Schasinglulu b report_exception /* Reserved */ 29*91f16700Schasinglulu b report_exception /* IRQ */ 30*91f16700Schasinglulu b report_exception /* FIQ */ 31*91f16700Schasinglulu 32*91f16700Schasinglulu /* ----------------------------------------------------- 33*91f16700Schasinglulu * bl1_entrypoint() is the entry point into the trusted 34*91f16700Schasinglulu * firmware code when a cpu is released from warm or 35*91f16700Schasinglulu * cold reset. 36*91f16700Schasinglulu * ----------------------------------------------------- 37*91f16700Schasinglulu */ 38*91f16700Schasinglulu 39*91f16700Schasinglulufunc bl1_entrypoint 40*91f16700Schasinglulu/* --------------------------------------------------------------------- 41*91f16700Schasinglulu* If the reset address is programmable then bl1_entrypoint() is 42*91f16700Schasinglulu* executed only on the cold boot path. Therefore, we can skip the warm 43*91f16700Schasinglulu* boot mailbox mechanism. 44*91f16700Schasinglulu* --------------------------------------------------------------------- 45*91f16700Schasinglulu*/ 46*91f16700Schasinglulu el3_entrypoint_common \ 47*91f16700Schasinglulu _init_sctlr=1 \ 48*91f16700Schasinglulu _warm_boot_mailbox=!PROGRAMMABLE_RESET_ADDRESS \ 49*91f16700Schasinglulu _secondary_cold_boot=!COLD_BOOT_SINGLE_CPU \ 50*91f16700Schasinglulu _init_memory=1 \ 51*91f16700Schasinglulu _init_c_runtime=1 \ 52*91f16700Schasinglulu _exception_vectors=bl1_vector_table \ 53*91f16700Schasinglulu _pie_fixup_size=0 54*91f16700Schasinglulu 55*91f16700Schasinglulu /* ----------------------------------------------------- 56*91f16700Schasinglulu * Perform BL1 setup 57*91f16700Schasinglulu * ----------------------------------------------------- 58*91f16700Schasinglulu */ 59*91f16700Schasinglulu bl bl1_setup 60*91f16700Schasinglulu 61*91f16700Schasinglulu /* ----------------------------------------------------- 62*91f16700Schasinglulu * Jump to main function. 63*91f16700Schasinglulu * ----------------------------------------------------- 64*91f16700Schasinglulu */ 65*91f16700Schasinglulu bl bl1_main 66*91f16700Schasinglulu 67*91f16700Schasinglulu /* ----------------------------------------------------- 68*91f16700Schasinglulu * Jump to next image. 69*91f16700Schasinglulu * ----------------------------------------------------- 70*91f16700Schasinglulu */ 71*91f16700Schasinglulu 72*91f16700Schasinglulu /* 73*91f16700Schasinglulu * Get the smc_context for next BL image, 74*91f16700Schasinglulu * program the gp/system registers and save it in `r4`. 75*91f16700Schasinglulu */ 76*91f16700Schasinglulu bl smc_get_next_ctx 77*91f16700Schasinglulu mov r4, r0 78*91f16700Schasinglulu 79*91f16700Schasinglulu /* Only turn-off MMU if going to secure world */ 80*91f16700Schasinglulu ldr r5, [r4, #SMC_CTX_SCR] 81*91f16700Schasinglulu tst r5, #SCR_NS_BIT 82*91f16700Schasinglulu bne skip_mmu_off 83*91f16700Schasinglulu 84*91f16700Schasinglulu /* 85*91f16700Schasinglulu * MMU needs to be disabled because both BL1 and BL2/BL2U execute 86*91f16700Schasinglulu * in PL1, and therefore share the same address space. 87*91f16700Schasinglulu * BL2/BL2U will initialize the address space according to its 88*91f16700Schasinglulu * own requirement. 89*91f16700Schasinglulu */ 90*91f16700Schasinglulu bl disable_mmu_icache_secure 91*91f16700Schasinglulu stcopr r0, TLBIALL 92*91f16700Schasinglulu dsb sy 93*91f16700Schasinglulu isb 94*91f16700Schasinglulu 95*91f16700Schasingluluskip_mmu_off: 96*91f16700Schasinglulu /* Restore smc_context from `r4` and exit secure monitor mode. */ 97*91f16700Schasinglulu mov r0, r4 98*91f16700Schasinglulu monitor_exit 99*91f16700Schasingluluendfunc bl1_entrypoint 100