1 /* 2 * Copyright (c) 2018-2023, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <platform_def.h> 10 11 #include <common/bl_common.h> 12 #include <common/debug.h> 13 #include <drivers/arm/ccn.h> 14 #include <plat/arm/common/plat_arm.h> 15 #include <plat/common/platform.h> 16 #include <drivers/arm/sbsa.h> 17 #include <sgi_base_platform_def.h> 18 19 #if SPM_MM 20 #include <services/spm_mm_partition.h> 21 #endif 22 23 #define SGI_MAP_FLASH0_RO MAP_REGION_FLAT(V2M_FLASH0_BASE,\ 24 V2M_FLASH0_SIZE, \ 25 MT_DEVICE | MT_RO | MT_SECURE) 26 /* 27 * Table of regions for different BL stages to map using the MMU. 28 * This doesn't include Trusted RAM as the 'mem_layout' argument passed to 29 * arm_configure_mmu_elx() will give the available subset of that. 30 * 31 * Replace or extend the below regions as required 32 */ 33 #if IMAGE_BL1 34 const mmap_region_t plat_arm_mmap[] = { 35 ARM_MAP_SHARED_RAM, 36 SGI_MAP_FLASH0_RO, 37 CSS_SGI_MAP_DEVICE, 38 SOC_CSS_MAP_DEVICE, 39 {0} 40 }; 41 #endif 42 #if IMAGE_BL2 43 const mmap_region_t plat_arm_mmap[] = { 44 ARM_MAP_SHARED_RAM, 45 SGI_MAP_FLASH0_RO, 46 #ifdef PLAT_ARM_MEM_PROT_ADDR 47 ARM_V2M_MAP_MEM_PROTECT, 48 #endif 49 CSS_SGI_MAP_DEVICE, 50 SOC_CSS_MAP_DEVICE, 51 ARM_MAP_NS_DRAM1, 52 #if CSS_SGI_CHIP_COUNT > 1 53 CSS_SGI_MAP_DEVICE_REMOTE_CHIP(1), 54 #endif 55 #if CSS_SGI_CHIP_COUNT > 2 56 CSS_SGI_MAP_DEVICE_REMOTE_CHIP(2), 57 #endif 58 #if CSS_SGI_CHIP_COUNT > 3 59 CSS_SGI_MAP_DEVICE_REMOTE_CHIP(3), 60 #endif 61 #if ARM_BL31_IN_DRAM 62 ARM_MAP_BL31_SEC_DRAM, 63 #endif 64 #if SPM_MM 65 ARM_SP_IMAGE_MMAP, 66 #endif 67 #if TRUSTED_BOARD_BOOT && !RESET_TO_BL2 68 ARM_MAP_BL1_RW, 69 #endif 70 {0} 71 }; 72 #endif 73 #if IMAGE_BL31 74 const mmap_region_t plat_arm_mmap[] = { 75 ARM_MAP_SHARED_RAM, 76 V2M_MAP_IOFPGA, 77 CSS_SGI_MAP_DEVICE, 78 #ifdef PLAT_ARM_MEM_PROT_ADDR 79 ARM_V2M_MAP_MEM_PROTECT, 80 #endif 81 SOC_CSS_MAP_DEVICE, 82 #if SPM_MM 83 ARM_SPM_BUF_EL3_MMAP, 84 #endif 85 {0} 86 }; 87 88 #if SPM_MM && defined(IMAGE_BL31) 89 const mmap_region_t plat_arm_secure_partition_mmap[] = { 90 PLAT_ARM_SECURE_MAP_SYSTEMREG, 91 PLAT_ARM_SECURE_MAP_NOR2, 92 SOC_PLATFORM_SECURE_UART, 93 PLAT_ARM_SECURE_MAP_DEVICE, 94 ARM_SP_IMAGE_MMAP, 95 ARM_SP_IMAGE_NS_BUF_MMAP, 96 #if ENABLE_FEAT_RAS && FFH_SUPPORT 97 CSS_SGI_SP_CPER_BUF_MMAP, 98 #endif 99 ARM_SP_IMAGE_RW_MMAP, 100 ARM_SPM_BUF_EL0_MMAP, 101 {0} 102 }; 103 #endif /* SPM_MM && defined(IMAGE_BL31) */ 104 #endif 105 106 ARM_CASSERT_MMAP 107 108 #if SPM_MM && defined(IMAGE_BL31) 109 /* 110 * Boot information passed to a secure partition during initialisation. Linear 111 * indices in MP information will be filled at runtime. 112 */ 113 static spm_mm_mp_info_t sp_mp_info[] = { 114 [0] = {0x81000000, 0}, 115 [1] = {0x81000100, 0}, 116 [2] = {0x81000200, 0}, 117 [3] = {0x81000300, 0}, 118 [4] = {0x81010000, 0}, 119 [5] = {0x81010100, 0}, 120 [6] = {0x81010200, 0}, 121 [7] = {0x81010300, 0}, 122 }; 123 124 const spm_mm_boot_info_t plat_arm_secure_partition_boot_info = { 125 .h.type = PARAM_SP_IMAGE_BOOT_INFO, 126 .h.version = VERSION_1, 127 .h.size = sizeof(spm_mm_boot_info_t), 128 .h.attr = 0, 129 .sp_mem_base = ARM_SP_IMAGE_BASE, 130 .sp_mem_limit = ARM_SP_IMAGE_LIMIT, 131 .sp_image_base = ARM_SP_IMAGE_BASE, 132 .sp_stack_base = PLAT_SP_IMAGE_STACK_BASE, 133 .sp_heap_base = ARM_SP_IMAGE_HEAP_BASE, 134 .sp_ns_comm_buf_base = PLAT_SP_IMAGE_NS_BUF_BASE, 135 .sp_shared_buf_base = PLAT_SPM_BUF_BASE, 136 .sp_image_size = ARM_SP_IMAGE_SIZE, 137 .sp_pcpu_stack_size = PLAT_SP_IMAGE_STACK_PCPU_SIZE, 138 .sp_heap_size = ARM_SP_IMAGE_HEAP_SIZE, 139 .sp_ns_comm_buf_size = PLAT_SP_IMAGE_NS_BUF_SIZE, 140 .sp_shared_buf_size = PLAT_SPM_BUF_SIZE, 141 .num_sp_mem_regions = ARM_SP_IMAGE_NUM_MEM_REGIONS, 142 .num_cpus = PLATFORM_CORE_COUNT, 143 .mp_info = &sp_mp_info[0], 144 }; 145 146 const struct mmap_region *plat_get_secure_partition_mmap(void *cookie) 147 { 148 return plat_arm_secure_partition_mmap; 149 } 150 151 const struct spm_mm_boot_info *plat_get_secure_partition_boot_info( 152 void *cookie) 153 { 154 return &plat_arm_secure_partition_boot_info; 155 } 156 #endif /* SPM_MM && defined(IMAGE_BL31) */ 157 158 #if TRUSTED_BOARD_BOOT 159 int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size) 160 { 161 assert(heap_addr != NULL); 162 assert(heap_size != NULL); 163 164 return arm_get_mbedtls_heap(heap_addr, heap_size); 165 } 166 #endif 167 168 void plat_arm_secure_wdt_start(void) 169 { 170 sbsa_wdog_start(SBSA_SECURE_WDOG_BASE, SBSA_SECURE_WDOG_TIMEOUT); 171 } 172 173 void plat_arm_secure_wdt_stop(void) 174 { 175 sbsa_wdog_stop(SBSA_SECURE_WDOG_BASE); 176 } 177