1 /* 2 * Copyright (c) 2020-2023, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <common/debug.h> 8 #include <drivers/arm/gic600_multichip.h> 9 #include <plat/arm/common/plat_arm.h> 10 #include <plat/common/platform.h> 11 #include <services/el3_spmc_ffa_memory.h> 12 #include <rdn2_ras.h> 13 #include <sgi_soc_platform_def_v2.h> 14 #include <sgi_plat.h> 15 16 #if defined(IMAGE_BL31) 17 #if (CSS_SGI_PLATFORM_VARIANT == 2) 18 static const mmap_region_t rdn2mc_dynamic_mmap[] = { 19 #if CSS_SGI_CHIP_COUNT > 1 20 ARM_MAP_SHARED_RAM_REMOTE_CHIP(1), 21 CSS_SGI_MAP_DEVICE_REMOTE_CHIP(1), 22 #endif 23 #if CSS_SGI_CHIP_COUNT > 2 24 ARM_MAP_SHARED_RAM_REMOTE_CHIP(2), 25 CSS_SGI_MAP_DEVICE_REMOTE_CHIP(2), 26 #endif 27 #if CSS_SGI_CHIP_COUNT > 3 28 ARM_MAP_SHARED_RAM_REMOTE_CHIP(3), 29 CSS_SGI_MAP_DEVICE_REMOTE_CHIP(3), 30 #endif 31 }; 32 #endif 33 34 #if (CSS_SGI_PLATFORM_VARIANT == 2) 35 static struct gic600_multichip_data rdn2mc_multichip_data __init = { 36 .rt_owner_base = PLAT_ARM_GICD_BASE, 37 .rt_owner = 0, 38 .chip_count = CSS_SGI_CHIP_COUNT, 39 .chip_addrs = { 40 PLAT_ARM_GICD_BASE >> 16, 41 #if CSS_SGI_CHIP_COUNT > 1 42 (PLAT_ARM_GICD_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(1)) >> 16, 43 #endif 44 #if CSS_SGI_CHIP_COUNT > 2 45 (PLAT_ARM_GICD_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(2)) >> 16, 46 #endif 47 #if CSS_SGI_CHIP_COUNT > 3 48 (PLAT_ARM_GICD_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(3)) >> 16, 49 #endif 50 }, 51 .spi_ids = { 52 {PLAT_ARM_GICD_BASE, 32, 511}, 53 #if CSS_SGI_CHIP_COUNT > 1 54 {PLAT_ARM_GICD_BASE, 512, 991}, 55 #endif 56 #if CSS_SGI_CHIP_COUNT > 2 57 {PLAT_ARM_GICD_BASE, 4096, 4575}, 58 #endif 59 #if CSS_SGI_CHIP_COUNT > 3 60 {PLAT_ARM_GICD_BASE, 4576, 5055}, 61 #endif 62 } 63 }; 64 #endif 65 66 #if (CSS_SGI_PLATFORM_VARIANT == 2) 67 static uintptr_t rdn2mc_multichip_gicr_frames[] = { 68 /* Chip 0's GICR Base */ 69 PLAT_ARM_GICR_BASE, 70 #if CSS_SGI_CHIP_COUNT > 1 71 /* Chip 1's GICR BASE */ 72 PLAT_ARM_GICR_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(1), 73 #endif 74 #if CSS_SGI_CHIP_COUNT > 2 75 /* Chip 2's GICR BASE */ 76 PLAT_ARM_GICR_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(2), 77 #endif 78 #if CSS_SGI_CHIP_COUNT > 3 79 /* Chip 3's GICR BASE */ 80 PLAT_ARM_GICR_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(3), 81 #endif 82 UL(0) /* Zero Termination */ 83 }; 84 #endif 85 #endif /* IMAGE_BL31 */ 86 87 unsigned int plat_arm_sgi_get_platform_id(void) 88 { 89 return mmio_read_32(SID_REG_BASE + SID_SYSTEM_ID_OFFSET) 90 & SID_SYSTEM_ID_PART_NUM_MASK; 91 } 92 93 unsigned int plat_arm_sgi_get_config_id(void) 94 { 95 return mmio_read_32(SID_REG_BASE + SID_SYSTEM_CFG_OFFSET); 96 } 97 98 unsigned int plat_arm_sgi_get_multi_chip_mode(void) 99 { 100 return (mmio_read_32(SID_REG_BASE + SID_NODE_ID_OFFSET) & 101 SID_MULTI_CHIP_MODE_MASK) >> 102 SID_MULTI_CHIP_MODE_SHIFT; 103 } 104 105 #if defined(IMAGE_BL31) 106 void bl31_platform_setup(void) 107 { 108 #if (CSS_SGI_PLATFORM_VARIANT == 2) 109 int ret; 110 unsigned int i; 111 112 if (plat_arm_sgi_get_multi_chip_mode() == 0) { 113 ERROR("Chip Count is set to %u but multi-chip mode is not " 114 "enabled\n", CSS_SGI_CHIP_COUNT); 115 panic(); 116 } else { 117 INFO("Enabling multi-chip support for RD-N2 variant\n"); 118 119 for (i = 0; i < ARRAY_SIZE(rdn2mc_dynamic_mmap); i++) { 120 ret = mmap_add_dynamic_region( 121 rdn2mc_dynamic_mmap[i].base_pa, 122 rdn2mc_dynamic_mmap[i].base_va, 123 rdn2mc_dynamic_mmap[i].size, 124 rdn2mc_dynamic_mmap[i].attr); 125 if (ret != 0) { 126 ERROR("Failed to add dynamic mmap entry for" 127 " i: %d " "(ret=%d)\n", i, ret); 128 panic(); 129 } 130 } 131 132 plat_arm_override_gicr_frames( 133 rdn2mc_multichip_gicr_frames); 134 gic600_multichip_init(&rdn2mc_multichip_data); 135 } 136 #endif 137 138 sgi_bl31_common_platform_setup(); 139 140 #if ENABLE_FEAT_RAS && FFH_SUPPORT 141 sgi_ras_platform_setup(&ras_config); 142 #endif 143 } 144 #endif /* IMAGE_BL31 */ 145 146 #if SPMC_AT_EL3 147 148 #define DATASTORE_SIZE 1024 149 150 __section("arm_el3_tzc_dram") uint8_t plat_spmc_shmem_datastore[DATASTORE_SIZE]; 151 152 int plat_spmc_shmem_datastore_get(uint8_t **datastore, size_t *size) 153 { 154 *datastore = plat_spmc_shmem_datastore; 155 *size = DATASTORE_SIZE; 156 return 0; 157 } 158 159 /* 160 * Add dummy implementations of memory management related platform hooks. 161 * Memory share/lend operation are not required on RdN2 platform. 162 */ 163 int plat_spmc_shmem_begin(struct ffa_mtd *desc) 164 { 165 return 0; 166 } 167 168 int plat_spmc_shmem_reclaim(struct ffa_mtd *desc) 169 { 170 return 0; 171 } 172 173 int plat_spmd_handle_group0_interrupt(uint32_t intid) 174 { 175 /* 176 * As of now, there are no sources of Group0 secure interrupt enabled 177 * for RDN2. 178 */ 179 (void)intid; 180 return -1; 181 } 182 #endif 183