1 /* 2 * Copyright (c) 2019-2023, Intel Corporation. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 #include <common/debug.h> 10 #include <drivers/delay_timer.h> 11 #include <lib/mmio.h> 12 #include <platform_def.h> 13 14 #include "socfpga_f2sdram_manager.h" 15 #include "socfpga_mailbox.h" 16 #include "socfpga_plat_def.h" 17 #include "socfpga_reset_manager.h" 18 #include "socfpga_system_manager.h" 19 20 void deassert_peripheral_reset(void) 21 { 22 mmio_clrbits_32(SOCFPGA_RSTMGR(PER1MODRST), 23 RSTMGR_FIELD(PER1, WATCHDOG0) | 24 RSTMGR_FIELD(PER1, WATCHDOG1) | 25 RSTMGR_FIELD(PER1, WATCHDOG2) | 26 RSTMGR_FIELD(PER1, WATCHDOG3) | 27 RSTMGR_FIELD(PER1, WATCHDOG4) | 28 RSTMGR_FIELD(PER1, L4SYSTIMER0) | 29 RSTMGR_FIELD(PER1, L4SYSTIMER1) | 30 RSTMGR_FIELD(PER1, SPTIMER0) | 31 RSTMGR_FIELD(PER1, SPTIMER1) | 32 RSTMGR_FIELD(PER1, I2C0) | 33 RSTMGR_FIELD(PER1, I2C1) | 34 RSTMGR_FIELD(PER1, I2C2) | 35 RSTMGR_FIELD(PER1, I2C3) | 36 RSTMGR_FIELD(PER1, I2C4) | 37 RSTMGR_FIELD(PER1, I3C0) | 38 RSTMGR_FIELD(PER1, I3C1) | 39 RSTMGR_FIELD(PER1, UART0) | 40 RSTMGR_FIELD(PER1, UART1) | 41 RSTMGR_FIELD(PER1, GPIO0) | 42 RSTMGR_FIELD(PER1, GPIO1)); 43 44 mmio_clrbits_32(SOCFPGA_RSTMGR(PER0MODRST), 45 RSTMGR_FIELD(PER0, SOFTPHY) | 46 RSTMGR_FIELD(PER0, EMAC0OCP) | 47 RSTMGR_FIELD(PER0, EMAC1OCP) | 48 RSTMGR_FIELD(PER0, EMAC2OCP) | 49 RSTMGR_FIELD(PER0, USB0OCP) | 50 RSTMGR_FIELD(PER0, USB1OCP) | 51 RSTMGR_FIELD(PER0, NANDOCP) | 52 RSTMGR_FIELD(PER0, SDMMCOCP) | 53 RSTMGR_FIELD(PER0, DMAOCP)); 54 55 mmio_clrbits_32(SOCFPGA_RSTMGR(PER0MODRST), 56 RSTMGR_FIELD(PER0, EMAC0) | 57 RSTMGR_FIELD(PER0, EMAC1) | 58 RSTMGR_FIELD(PER0, EMAC2) | 59 RSTMGR_FIELD(PER0, USB0) | 60 RSTMGR_FIELD(PER0, USB1) | 61 RSTMGR_FIELD(PER0, NAND) | 62 RSTMGR_FIELD(PER0, SDMMC) | 63 RSTMGR_FIELD(PER0, DMA) | 64 RSTMGR_FIELD(PER0, SPIM0) | 65 RSTMGR_FIELD(PER0, SPIM1) | 66 RSTMGR_FIELD(PER0, SPIS0) | 67 RSTMGR_FIELD(PER0, SPIS1) | 68 RSTMGR_FIELD(PER0, EMACPTP) | 69 RSTMGR_FIELD(PER0, DMAIF0) | 70 RSTMGR_FIELD(PER0, DMAIF1) | 71 RSTMGR_FIELD(PER0, DMAIF2) | 72 RSTMGR_FIELD(PER0, DMAIF3) | 73 RSTMGR_FIELD(PER0, DMAIF4) | 74 RSTMGR_FIELD(PER0, DMAIF5) | 75 RSTMGR_FIELD(PER0, DMAIF6) | 76 RSTMGR_FIELD(PER0, DMAIF7)); 77 78 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX 79 mmio_clrbits_32(SOCFPGA_RSTMGR(BRGMODRST), 80 RSTMGR_FIELD(BRG, MPFE)); 81 #endif 82 } 83 84 void config_hps_hs_before_warm_reset(void) 85 { 86 uint32_t or_mask = 0; 87 88 or_mask |= RSTMGR_HDSKEN_EMIF_FLUSH; 89 or_mask |= RSTMGR_HDSKEN_FPGAHSEN; 90 or_mask |= RSTMGR_HDSKEN_ETRSTALLEN; 91 or_mask |= RSTMGR_HDSKEN_LWS2F_FLUSH; 92 or_mask |= RSTMGR_HDSKEN_L3NOC_DBG; 93 or_mask |= RSTMGR_HDSKEN_DEBUG_L3NOC; 94 95 mmio_setbits_32(SOCFPGA_RSTMGR(HDSKEN), or_mask); 96 } 97 98 static int poll_idle_status(uint32_t addr, uint32_t mask, uint32_t match, uint32_t delay_ms) 99 { 100 int time_out = delay_ms; 101 102 while (time_out-- > 0) { 103 104 if ((mmio_read_32(addr) & mask) == match) { 105 return 0; 106 } 107 udelay(1000); 108 } 109 return -ETIMEDOUT; 110 } 111 112 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 113 static int poll_idle_status_by_counter(uint32_t addr, uint32_t mask, 114 uint32_t match, uint32_t delay_ms) 115 { 116 int time_out = delay_ms; 117 118 while (time_out-- > 0) { 119 120 if ((mmio_read_32(addr) & mask) == match) { 121 return 0; 122 } 123 124 /* ToDo: Shall use udelay for product release */ 125 for (int i = 0; i < 2000; i++) { 126 /* dummy delay */ 127 } 128 } 129 return -ETIMEDOUT; 130 } 131 #endif 132 133 static int poll_idle_status_by_clkcycles(uint32_t addr, uint32_t mask, 134 uint32_t match, uint32_t delay_clk_cycles) 135 { 136 int time_out = delay_clk_cycles; 137 138 while (time_out-- > 0) { 139 140 if ((mmio_read_32(addr) & mask) == match) { 141 return 0; 142 } 143 udelay(1); 144 } 145 return -ETIMEDOUT; 146 } 147 148 static void socfpga_s2f_bridge_mask(uint32_t mask, 149 uint32_t *brg_mask, 150 uint32_t *noc_mask) 151 { 152 *brg_mask = 0; 153 *noc_mask = 0; 154 155 if ((mask & SOC2FPGA_MASK) != 0U) { 156 *brg_mask |= RSTMGR_FIELD(BRG, SOC2FPGA); 157 *noc_mask |= IDLE_DATA_SOC2FPGA; 158 } 159 160 if ((mask & LWHPS2FPGA_MASK) != 0U) { 161 *brg_mask |= RSTMGR_FIELD(BRG, LWHPS2FPGA); 162 *noc_mask |= IDLE_DATA_LWSOC2FPGA; 163 } 164 } 165 166 static void socfpga_f2s_bridge_mask(uint32_t mask, 167 uint32_t *brg_mask, 168 uint32_t *f2s_idlereq, 169 uint32_t *f2s_force_drain, 170 uint32_t *f2s_en, 171 uint32_t *f2s_idleack, 172 uint32_t *f2s_respempty, 173 uint32_t *f2s_cmdidle) 174 { 175 *brg_mask = 0; 176 *f2s_idlereq = 0; 177 *f2s_force_drain = 0; 178 *f2s_en = 0; 179 *f2s_idleack = 0; 180 *f2s_respempty = 0; 181 *f2s_cmdidle = 0; 182 183 #if PLATFORM_MODEL == PLAT_SOCFPGA_STRATIX10 184 if ((mask & FPGA2SOC_MASK) != 0U) { 185 *brg_mask |= RSTMGR_FIELD(BRG, FPGA2SOC); 186 } 187 if ((mask & F2SDRAM0_MASK) != 0U) { 188 *brg_mask |= RSTMGR_FIELD(BRG, F2SSDRAM0); 189 *f2s_idlereq |= FLAGOUTSETCLR_F2SDRAM0_IDLEREQ; 190 *f2s_force_drain |= FLAGOUTSETCLR_F2SDRAM0_FORCE_DRAIN; 191 *f2s_en |= FLAGOUTSETCLR_F2SDRAM0_ENABLE; 192 *f2s_idleack |= FLAGINSTATUS_F2SDRAM0_IDLEACK; 193 *f2s_respempty |= FLAGINSTATUS_F2SDRAM0_RESPEMPTY; 194 *f2s_cmdidle |= FLAGINSTATUS_F2SDRAM0_CMDIDLE; 195 } 196 if ((mask & F2SDRAM1_MASK) != 0U) { 197 *brg_mask |= RSTMGR_FIELD(BRG, F2SSDRAM1); 198 *f2s_idlereq |= FLAGOUTSETCLR_F2SDRAM1_IDLEREQ; 199 *f2s_force_drain |= FLAGOUTSETCLR_F2SDRAM1_FORCE_DRAIN; 200 *f2s_en |= FLAGOUTSETCLR_F2SDRAM1_ENABLE; 201 *f2s_idleack |= FLAGINSTATUS_F2SDRAM1_IDLEACK; 202 *f2s_respempty |= FLAGINSTATUS_F2SDRAM1_RESPEMPTY; 203 *f2s_cmdidle |= FLAGINSTATUS_F2SDRAM1_CMDIDLE; 204 } 205 if ((mask & F2SDRAM2_MASK) != 0U) { 206 *brg_mask |= RSTMGR_FIELD(BRG, F2SSDRAM2); 207 *f2s_idlereq |= FLAGOUTSETCLR_F2SDRAM2_IDLEREQ; 208 *f2s_force_drain |= FLAGOUTSETCLR_F2SDRAM2_FORCE_DRAIN; 209 *f2s_en |= FLAGOUTSETCLR_F2SDRAM2_ENABLE; 210 *f2s_idleack |= FLAGINSTATUS_F2SDRAM2_IDLEACK; 211 *f2s_respempty |= FLAGINSTATUS_F2SDRAM2_RESPEMPTY; 212 *f2s_cmdidle |= FLAGINSTATUS_F2SDRAM2_CMDIDLE; 213 } 214 #elif PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 215 if (mask & FPGA2SOC_MASK) { 216 *brg_mask |= RSTMGR_FIELD(BRG, FPGA2SOC); 217 *f2s_idlereq |= FLAGOUTSETCLR_F2SDRAM0_IDLEREQ; 218 *f2s_force_drain |= FLAGOUTSETCLR_F2SDRAM0_FORCE_DRAIN; 219 *f2s_en |= FLAGOUTSETCLR_F2SDRAM0_ENABLE; 220 *f2s_idleack |= FLAGINSTATUS_F2SDRAM0_IDLEACK; 221 *f2s_respempty |= FLAGINSTATUS_F2SDRAM0_RESPEMPTY; 222 } 223 if (mask & F2SDRAM0_MASK) { 224 *brg_mask |= RSTMGR_FIELD(BRG, F2SSDRAM0); 225 *f2s_idlereq |= FLAGOUTSETCLR_F2SDRAM0_IDLEREQ; 226 *f2s_force_drain |= FLAGOUTSETCLR_F2SDRAM0_FORCE_DRAIN; 227 *f2s_en |= FLAGOUTSETCLR_F2SDRAM0_ENABLE; 228 *f2s_idleack |= FLAGINSTATUS_F2SDRAM0_IDLEACK; 229 *f2s_respempty |= FLAGINSTATUS_F2SDRAM0_RESPEMPTY; 230 } 231 if (mask & F2SDRAM1_MASK) { 232 *brg_mask |= RSTMGR_FIELD(BRG, F2SSDRAM1); 233 *f2s_idlereq |= FLAGOUTSETCLR_F2SDRAM1_IDLEREQ; 234 *f2s_force_drain |= FLAGOUTSETCLR_F2SDRAM1_FORCE_DRAIN; 235 *f2s_en |= FLAGOUTSETCLR_F2SDRAM1_ENABLE; 236 *f2s_idleack |= FLAGINSTATUS_F2SDRAM1_IDLEACK; 237 *f2s_respempty |= FLAGINSTATUS_F2SDRAM1_RESPEMPTY; 238 } 239 if (mask & F2SDRAM2_MASK) { 240 *brg_mask |= RSTMGR_FIELD(BRG, F2SSDRAM2); 241 *f2s_idlereq |= FLAGOUTSETCLR_F2SDRAM2_IDLEREQ; 242 *f2s_force_drain |= FLAGOUTSETCLR_F2SDRAM2_FORCE_DRAIN; 243 *f2s_en |= FLAGOUTSETCLR_F2SDRAM2_ENABLE; 244 *f2s_idleack |= FLAGINSTATUS_F2SDRAM2_IDLEACK; 245 *f2s_respempty |= FLAGINSTATUS_F2SDRAM2_RESPEMPTY; 246 } 247 #else 248 if ((mask & FPGA2SOC_MASK) != 0U) { 249 *brg_mask |= RSTMGR_FIELD(BRG, FPGA2SOC); 250 *f2s_idlereq |= FLAGOUTSETCLR_F2SDRAM0_IDLEREQ; 251 *f2s_force_drain |= FLAGOUTSETCLR_F2SDRAM0_FORCE_DRAIN; 252 *f2s_en |= FLAGOUTSETCLR_F2SDRAM0_ENABLE; 253 *f2s_idleack |= FLAGINSTATUS_F2SDRAM0_IDLEACK; 254 *f2s_respempty |= FLAGINSTATUS_F2SDRAM0_RESPEMPTY; 255 *f2s_cmdidle |= FLAGINSTATUS_F2SDRAM0_CMDIDLE; 256 } 257 #endif 258 } 259 260 int socfpga_bridges_reset(uint32_t mask) 261 { 262 int ret = 0; 263 int timeout = 300; 264 uint32_t brg_mask = 0; 265 uint32_t noc_mask = 0; 266 uint32_t f2s_idlereq = 0; 267 uint32_t f2s_force_drain = 0; 268 uint32_t f2s_en = 0; 269 uint32_t f2s_idleack = 0; 270 uint32_t f2s_respempty = 0; 271 uint32_t f2s_cmdidle = 0; 272 273 /* Reset s2f bridge */ 274 socfpga_s2f_bridge_mask(mask, &brg_mask, &noc_mask); 275 if (brg_mask) { 276 if (mask & SOC2FPGA_MASK) { 277 /* Request handshake with SOC2FPGA bridge to clear traffic */ 278 mmio_setbits_32(SOCFPGA_RSTMGR(HDSKREQ), 279 RSTMGR_HDSKREQ_S2F_FLUSH); 280 281 /* Wait for bridge to idle status */ 282 ret = poll_idle_status(SOCFPGA_RSTMGR(HDSKACK), 283 RSTMGR_HDSKACK_S2F_FLUSH, 284 RSTMGR_HDSKACK_S2F_FLUSH, 300); 285 } 286 287 if (mask & LWHPS2FPGA_MASK) { 288 /* Request handshake with LWSOC2FPGA bridge to clear traffic */ 289 mmio_setbits_32(SOCFPGA_RSTMGR(HDSKREQ), 290 RSTMGR_HDSKREQ_LWS2F_FLUSH); 291 292 /* Wait for bridge to idle status */ 293 ret = poll_idle_status(SOCFPGA_RSTMGR(HDSKACK), 294 RSTMGR_HDSKACK_LWS2F_FLUSH, 295 RSTMGR_HDSKACK_LWS2F_FLUSH, 300); 296 } 297 298 if (ret < 0) { 299 ERROR("S2F Bridge reset: Timeout waiting for idle ack\n"); 300 assert(false); 301 } 302 303 /* Assert reset to bridge */ 304 mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST), 305 brg_mask); 306 307 /* Clear idle requests to bridge */ 308 if (mask & SOC2FPGA_MASK) { 309 mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ), 310 RSTMGR_HDSKREQ_S2F_FLUSH); 311 } 312 313 if (mask & LWHPS2FPGA_MASK) { 314 mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ), 315 RSTMGR_HDSKREQ_LWS2F_FLUSH); 316 } 317 318 /* When FPGA reconfig is complete */ 319 mmio_clrbits_32(SOCFPGA_RSTMGR(BRGMODRST), brg_mask); 320 } 321 322 /* Reset f2s bridge */ 323 socfpga_f2s_bridge_mask(mask, &brg_mask, &f2s_idlereq, 324 &f2s_force_drain, &f2s_en, 325 &f2s_idleack, &f2s_respempty, 326 &f2s_cmdidle); 327 328 if (brg_mask) { 329 mmio_setbits_32(SOCFPGA_RSTMGR(HDSKEN), 330 RSTMGR_HDSKEN_FPGAHSEN); 331 332 mmio_setbits_32(SOCFPGA_RSTMGR(HDSKREQ), 333 RSTMGR_HDSKREQ_FPGAHSREQ); 334 335 ret = poll_idle_status(SOCFPGA_RSTMGR(HDSKACK), 336 RSTMGR_HDSKACK_FPGAHSREQ, 337 RSTMGR_HDSKACK_FPGAHSREQ, 300); 338 339 if (ret < 0) { 340 ERROR("F2S Bridge disable: Timeout waiting for idle req\n"); 341 assert(false); 342 } 343 344 /* Disable f2s bridge */ 345 mmio_clrbits_32(SOCFPGA_F2SDRAMMGR(SIDEBANDMGR_FLAGOUTSET0), 346 f2s_en); 347 udelay(5); 348 349 mmio_setbits_32(SOCFPGA_F2SDRAMMGR(SIDEBANDMGR_FLAGOUTSET0), 350 f2s_force_drain); 351 udelay(5); 352 353 do { 354 /* Read response queue status to ensure it is empty */ 355 uint32_t idle_status; 356 357 idle_status = mmio_read_32(SOCFPGA_F2SDRAMMGR( 358 SIDEBANDMGR_FLAGINSTATUS0)); 359 if (idle_status & f2s_respempty) { 360 idle_status = mmio_read_32(SOCFPGA_F2SDRAMMGR( 361 SIDEBANDMGR_FLAGINSTATUS0)); 362 if (idle_status & f2s_respempty) { 363 break; 364 } 365 } 366 udelay(1000); 367 } while (timeout-- > 0); 368 369 /* Assert reset to f2s bridge */ 370 mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST), 371 brg_mask); 372 373 /* Clear idle request to FPGA */ 374 mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ), 375 RSTMGR_HDSKREQ_FPGAHSREQ); 376 377 /* Clear idle request to MPFE */ 378 mmio_setbits_32(SOCFPGA_F2SDRAMMGR(SIDEBANDMGR_FLAGOUTCLR0), 379 f2s_idlereq); 380 381 /* When FPGA reconfig is complete */ 382 mmio_clrbits_32(SOCFPGA_RSTMGR(BRGMODRST), brg_mask); 383 384 /* Enable f2s bridge */ 385 mmio_clrbits_32(SOCFPGA_F2SDRAMMGR(SIDEBANDMGR_FLAGOUTSET0), 386 f2s_idlereq); 387 388 ret = poll_idle_status(SOCFPGA_F2SDRAMMGR( 389 SIDEBANDMGR_FLAGINSTATUS0), f2s_idleack, 0, 300); 390 if (ret < 0) { 391 ERROR("F2S bridge enable: Timeout waiting for idle ack"); 392 assert(false); 393 } 394 395 mmio_clrbits_32(SOCFPGA_F2SDRAMMGR(SIDEBANDMGR_FLAGOUTSET0), 396 f2s_force_drain); 397 udelay(5); 398 399 mmio_setbits_32(SOCFPGA_F2SDRAMMGR(SIDEBANDMGR_FLAGOUTSET0), 400 f2s_en); 401 udelay(5); 402 } 403 404 return ret; 405 } 406 407 int socfpga_bridges_enable(uint32_t mask) 408 { 409 int ret = 0; 410 uint32_t brg_mask = 0; 411 uint32_t noc_mask = 0; 412 uint32_t f2s_idlereq = 0; 413 uint32_t f2s_force_drain = 0; 414 uint32_t f2s_en = 0; 415 uint32_t f2s_idleack = 0; 416 uint32_t f2s_respempty = 0; 417 uint32_t f2s_cmdidle = 0; 418 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 419 uint32_t delay = 0; 420 #endif 421 422 /* Enable s2f bridge */ 423 socfpga_s2f_bridge_mask(mask, &brg_mask, &noc_mask); 424 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 425 /* Enable SOC2FPGA bridge */ 426 if (brg_mask & RSTMGR_BRGMODRSTMASK_SOC2FPGA) { 427 /* Write Reset Manager hdskreq[soc2fpga_flush_req] = 1 */ 428 NOTICE("Set S2F hdskreq ...\n"); 429 mmio_setbits_32(SOCFPGA_RSTMGR(HDSKREQ), 430 RSTMGR_HDSKREQ_SOC2FPGAREQ); 431 432 /* Read Reset Manager hdskack[soc2fpga] = 1 */ 433 ret = poll_idle_status_by_counter(SOCFPGA_RSTMGR(HDSKACK), 434 RSTMGR_HDSKACK_SOC2FPGAACK, RSTMGR_HDSKACK_SOC2FPGAACK, 435 300); 436 437 if (ret < 0) { 438 ERROR("S2F bridge enable: Timeout hdskack\n"); 439 } 440 441 /* Write Reset Manager hdskreq[soc2fpga_flush_req] = 0 */ 442 NOTICE("Clear S2F hdskreq ...\n"); 443 mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ), 444 RSTMGR_HDSKREQ_SOC2FPGAREQ); 445 446 /* Write Reset Manager brgmodrst[soc2fpga] = 1 */ 447 NOTICE("Assert S2F ...\n"); 448 mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST), 449 RSTMGR_BRGMODRST_SOC2FPGA); 450 451 /* ToDo: Shall use udelay for product release */ 452 for (delay = 0; delay < 1000; delay++) { 453 /* dummy delay */ 454 } 455 456 /* Write Reset Manager brgmodrst[soc2fpga] = 0 */ 457 NOTICE("Deassert S2F ...\n"); 458 mmio_clrbits_32(SOCFPGA_RSTMGR(BRGMODRST), 459 RSTMGR_BRGMODRST_SOC2FPGA); 460 } 461 462 /* Enable LWSOC2FPGA bridge */ 463 if (brg_mask & RSTMGR_BRGMODRSTMASK_LWHPS2FPGA) { 464 /* Write Reset Manager hdskreq[lwsoc2fpga_flush_req] = 1 */ 465 NOTICE("Set LWS2F hdskreq ...\n"); 466 mmio_setbits_32(SOCFPGA_RSTMGR(HDSKREQ), 467 RSTMGR_HDSKREQ_LWSOC2FPGAREQ); 468 469 /* Read Reset Manager hdskack[lwsoc2fpga] = 1 */ 470 ret = poll_idle_status_by_counter(SOCFPGA_RSTMGR(HDSKACK), 471 RSTMGR_HDSKACK_LWSOC2FPGAACK, RSTMGR_HDSKACK_LWSOC2FPGAACK, 472 300); 473 474 if (ret < 0) { 475 ERROR("LWS2F bridge enable: Timeout hdskack\n"); 476 } 477 478 /* Write Reset Manager hdskreq[lwsoc2fpga_flush_req] = 0 */ 479 NOTICE("Clear LWS2F hdskreq ...\n"); 480 mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ), 481 RSTMGR_HDSKREQ_LWSOC2FPGAREQ); 482 483 /* Write Reset Manager brgmodrst[lwsoc2fpga] = 1 */ 484 NOTICE("Assert LWS2F ...\n"); 485 mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST), 486 RSTMGR_BRGMODRST_LWHPS2FPGA); 487 488 /* ToDo: Shall use udelay for product release */ 489 for (delay = 0; delay < 1000; delay++) { 490 /* dummy delay */ 491 } 492 493 /* Write Reset Manager brgmodrst[lwsoc2fpga] = 0 */ 494 NOTICE("Deassert LWS2F ...\n"); 495 mmio_clrbits_32(SOCFPGA_RSTMGR(BRGMODRST), 496 RSTMGR_BRGMODRST_LWHPS2FPGA); 497 } 498 #else 499 if (brg_mask != 0U) { 500 /* Clear idle request */ 501 mmio_setbits_32(SOCFPGA_SYSMGR(NOC_IDLEREQ_CLR), 502 noc_mask); 503 504 /* De-assert all bridges */ 505 mmio_clrbits_32(SOCFPGA_RSTMGR(BRGMODRST), brg_mask); 506 507 /* Wait until idle ack becomes 0 */ 508 ret = poll_idle_status(SOCFPGA_SYSMGR(NOC_IDLEACK), 509 noc_mask, 0, 300); 510 if (ret < 0) { 511 ERROR("S2F bridge enable: Timeout idle ack\n"); 512 } 513 } 514 #endif 515 516 /* Enable f2s bridge */ 517 socfpga_f2s_bridge_mask(mask, &brg_mask, &f2s_idlereq, 518 &f2s_force_drain, &f2s_en, 519 &f2s_idleack, &f2s_respempty, &f2s_cmdidle); 520 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 521 /* Enable FPGA2SOC bridge */ 522 if (brg_mask & RSTMGR_BRGMODRSTMASK_FPGA2SOC) { 523 /* Write Reset Manager hdsken[fpgahsen] = 1 */ 524 NOTICE("Set FPGA hdsken(fpgahsen) ...\n"); 525 mmio_setbits_32(SOCFPGA_RSTMGR(HDSKEN), RSTMGR_HDSKEN_FPGAHSEN); 526 527 /* Write Reset Manager hdskreq[fpgahsreq] = 1 */ 528 NOTICE("Set FPGA hdskreq(fpgahsreq) ...\n"); 529 mmio_setbits_32(SOCFPGA_RSTMGR(HDSKREQ), RSTMGR_HDSKREQ_FPGAHSREQ); 530 531 /* Read Reset Manager hdskack[fpgahsack] = 1 */ 532 NOTICE("Get FPGA hdskack(fpgahsack) ...\n"); 533 ret = poll_idle_status_by_counter(SOCFPGA_RSTMGR(HDSKACK), 534 RSTMGR_HDSKACK_FPGAHSACK, RSTMGR_HDSKACK_FPGAHSACK, 535 300); 536 537 if (ret < 0) { 538 ERROR("FPGA bridge fpga handshake fpgahsreq: Timeout\n"); 539 } 540 541 /* Write Reset Manager hdskreq[f2s_flush_req] = 1 */ 542 NOTICE("Set F2S hdskreq(f2s_flush_req) ...\n"); 543 mmio_setbits_32(SOCFPGA_RSTMGR(HDSKREQ), 544 RSTMGR_HDSKREQ_FPGA2SOCREQ); 545 546 /* Read Reset Manager hdskack[f2s_flush_ack] = 1 */ 547 NOTICE("Get F2S hdskack(f2s_flush_ack) ...\n"); 548 ret = poll_idle_status_by_counter(SOCFPGA_RSTMGR(HDSKACK), 549 RSTMGR_HDSKACK_FPGA2SOCACK, RSTMGR_HDSKACK_FPGA2SOCACK, 550 300); 551 552 if (ret < 0) { 553 ERROR("F2S bridge fpga handshake f2sdram_flush_req: Timeout\n"); 554 } 555 556 /* Write Reset Manager hdskreq[fpgahsreq] = 1 */ 557 NOTICE("Clear FPGA hdskreq(fpgahsreq) ...\n"); 558 mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ), RSTMGR_HDSKREQ_FPGAHSREQ); 559 560 /* Write Reset Manager hdskreq[f2s_flush_req] = 1 */ 561 NOTICE("Clear F2S hdskreq(f2s_flush_req) ...\n"); 562 mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ), 563 RSTMGR_HDSKREQ_FPGA2SOCREQ); 564 565 /* Read Reset Manager hdskack[f2s_flush_ack] = 0 */ 566 NOTICE("Get F2SDRAM hdskack(f2s_flush_ack) ...\n"); 567 ret = poll_idle_status_by_counter(SOCFPGA_RSTMGR(HDSKACK), 568 RSTMGR_HDSKACK_FPGA2SOCACK, RSTMGR_HDSKACK_FPGA2SOCACK_DASRT, 569 300); 570 571 if (ret < 0) { 572 ERROR("F2S bridge fpga handshake f2s_flush_ack: Timeout\n"); 573 } 574 575 /* Read Reset Manager hdskack[fpgahsack] = 0 */ 576 NOTICE("Get FPGA hdskack(fpgahsack) ...\n"); 577 ret = poll_idle_status_by_counter(SOCFPGA_RSTMGR(HDSKACK), 578 RSTMGR_HDSKACK_FPGAHSACK, RSTMGR_HDSKACK_FPGAHSACK_DASRT, 579 300); 580 581 if (ret < 0) { 582 ERROR("F2S bridge fpga handshake fpgahsack: Timeout\n"); 583 } 584 585 /* Write Reset Manager brgmodrst[fpga2soc] = 1 */ 586 NOTICE("Assert F2S ...\n"); 587 mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST), RSTMGR_BRGMODRST_FPGA2SOC); 588 589 /* ToDo: Shall use udelay for product release */ 590 for (delay = 0; delay < 1000; delay++) { 591 /* dummy delay */ 592 } 593 594 /* Write Reset Manager brgmodrst[fpga2soc] = 0 */ 595 NOTICE("Deassert F2S ...\n"); 596 mmio_clrbits_32(SOCFPGA_RSTMGR(BRGMODRST), RSTMGR_BRGMODRST_FPGA2SOC); 597 598 /* Write System Manager f2s bridge control register[f2soc_enable] = 1 */ 599 NOTICE("Deassert F2S f2soc_enable ...\n"); 600 mmio_setbits_32(SOCFPGA_SYSMGR(F2S_BRIDGE_CTRL), 601 SYSMGR_F2S_BRIDGE_CTRL_EN); 602 } 603 604 /* Enable FPGA2SDRAM bridge */ 605 if (brg_mask & RSTMGR_BRGMODRSTMASK_F2SDRAM0) { 606 /* Write Reset Manager hdsken[fpgahsen] = 1 */ 607 NOTICE("Set F2SDRAM hdsken(fpgahsen) ...\n"); 608 mmio_setbits_32(SOCFPGA_RSTMGR(HDSKEN), RSTMGR_HDSKEN_FPGAHSEN); 609 610 /* Write Reset Manager hdskreq[fpgahsreq] = 1 */ 611 NOTICE("Set F2SDRAM hdskreq(fpgahsreq) ...\n"); 612 mmio_setbits_32(SOCFPGA_RSTMGR(HDSKREQ), RSTMGR_HDSKREQ_FPGAHSREQ); 613 614 /* Read Reset Manager hdskack[fpgahsack] = 1 */ 615 NOTICE("Get F2SDRAM hdskack(fpgahsack) ...\n"); 616 ret = poll_idle_status_by_counter(SOCFPGA_RSTMGR(HDSKACK), 617 RSTMGR_HDSKACK_FPGAHSACK, RSTMGR_HDSKACK_FPGAHSACK, 618 300); 619 620 if (ret < 0) { 621 ERROR("F2SDRAM bridge fpga handshake fpgahsreq: Timeout\n"); 622 } 623 624 /* Write Reset Manager hdskreq[f2sdram_flush_req] = 1 */ 625 NOTICE("Set F2SDRAM hdskreq(f2sdram_flush_req) ...\n"); 626 mmio_setbits_32(SOCFPGA_RSTMGR(HDSKREQ), 627 RSTMGR_HDSKREQ_F2SDRAM0REQ); 628 629 /* Read Reset Manager hdskack[f2sdram_flush_ack] = 1 */ 630 NOTICE("Get F2SDRAM hdskack(f2sdram_flush_ack) ...\n"); 631 ret = poll_idle_status_by_counter(SOCFPGA_RSTMGR(HDSKACK), 632 RSTMGR_HDSKACK_F2SDRAM0ACK, RSTMGR_HDSKACK_F2SDRAM0ACK, 633 300); 634 635 if (ret < 0) { 636 ERROR("F2SDRAM bridge fpga handshake f2sdram_flush_req: Timeout\n"); 637 } 638 639 /* Write Reset Manager hdskreq[fpgahsreq] = 1 */ 640 NOTICE("Clear F2SDRAM hdskreq(fpgahsreq) ...\n"); 641 mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ), RSTMGR_HDSKREQ_FPGAHSREQ); 642 643 /* Write Reset Manager hdskreq[f2sdram_flush_req] = 1 */ 644 NOTICE("Clear F2SDRAM hdskreq(f2sdram_flush_req) ...\n"); 645 mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ), RSTMGR_HDSKREQ_F2SDRAM0REQ); 646 647 /* Read Reset Manager hdskack[f2sdram_flush_ack] = 0 */ 648 NOTICE("Get F2SDRAM hdskack(f2sdram_flush_ack) ...\n"); 649 ret = poll_idle_status_by_counter(SOCFPGA_RSTMGR(HDSKACK), 650 RSTMGR_HDSKACK_F2SDRAM0ACK, RSTMGR_HDSKACK_F2SDRAM0ACK_DASRT, 651 300); 652 653 if (ret < 0) { 654 ERROR("F2SDRAM bridge fpga handshake f2sdram_flush_ack: Timeout\n"); 655 } 656 657 /* Read Reset Manager hdskack[fpgahsack] = 0 */ 658 NOTICE("Get F2SDRAM hdskack(fpgahsack) ...\n"); 659 ret = poll_idle_status_by_counter(SOCFPGA_RSTMGR(HDSKACK), 660 RSTMGR_HDSKACK_FPGAHSACK, RSTMGR_HDSKACK_FPGAHSACK_DASRT, 661 300); 662 663 if (ret < 0) { 664 ERROR("F2SDRAM bridge fpga handshake fpgahsack: Timeout\n"); 665 } 666 667 /* Write Reset Manager brgmodrst[fpga2sdram] = 1 */ 668 NOTICE("Assert F2SDRAM ...\n"); 669 mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST), 670 RSTMGR_BRGMODRST_F2SSDRAM0); 671 672 /* ToDo: Shall use udelay for product release */ 673 for (delay = 0; delay < 1000; delay++) { 674 /* dummy delay */ 675 } 676 677 /* Write Reset Manager brgmodrst[fpga2sdram] = 0 */ 678 NOTICE("Deassert F2SDRAM ...\n"); 679 mmio_clrbits_32(SOCFPGA_RSTMGR(BRGMODRST), 680 RSTMGR_BRGMODRST_F2SSDRAM0); 681 682 /* 683 * Clear fpga2sdram_manager_main_SidebandManager_FlagOutClr0 684 * f2s_ready_latency_enable 685 */ 686 NOTICE("Clear F2SDRAM f2s_ready_latency_enable ...\n"); 687 mmio_setbits_32(SOCFPGA_F2SDRAMMGR(SIDEBANDMGR_FLAGOUTCLR0), 688 FLAGOUTCLR0_F2SDRAM0_ENABLE); 689 } 690 #else 691 if (brg_mask != 0U) { 692 mmio_clrbits_32(SOCFPGA_RSTMGR(BRGMODRST), brg_mask); 693 694 mmio_setbits_32(SOCFPGA_F2SDRAMMGR(SIDEBANDMGR_FLAGOUTCLR0), 695 f2s_idlereq); 696 697 ret = poll_idle_status(SOCFPGA_F2SDRAMMGR(SIDEBANDMGR_FLAGINSTATUS0), 698 f2s_idleack, 0, 300); 699 700 if (ret < 0) { 701 ERROR("F2S bridge enable: Timeout idle ack"); 702 } 703 704 /* Clear the force drain */ 705 mmio_setbits_32(SOCFPGA_F2SDRAMMGR(SIDEBANDMGR_FLAGOUTCLR0), 706 f2s_force_drain); 707 udelay(5); 708 709 mmio_setbits_32(SOCFPGA_F2SDRAMMGR(SIDEBANDMGR_FLAGOUTSET0), 710 f2s_en); 711 udelay(5); 712 } 713 #endif 714 return ret; 715 } 716 717 int socfpga_bridge_nongraceful_disable(uint32_t mask) 718 { 719 int ret = 0; 720 int timeout = 1000; 721 uint32_t brg_mask = 0; 722 uint32_t f2s_idlereq = 0; 723 uint32_t f2s_force_drain = 0; 724 uint32_t f2s_en = 0; 725 uint32_t f2s_idleack = 0; 726 uint32_t f2s_respempty = 0; 727 uint32_t f2s_cmdidle = 0; 728 729 socfpga_f2s_bridge_mask(mask, &brg_mask, &f2s_idlereq, 730 &f2s_force_drain, &f2s_en, 731 &f2s_idleack, &f2s_respempty, &f2s_cmdidle); 732 733 mmio_setbits_32(SOCFPGA_F2SDRAMMGR(SIDEBANDMGR_FLAGOUTSET0), 734 f2s_idlereq); 735 736 /* Time out Error - Bus is still active */ 737 /* Performing a non-graceful shutdown with Force drain */ 738 mmio_setbits_32(SOCFPGA_F2SDRAMMGR(SIDEBANDMGR_FLAGOUTSET0), 739 f2s_force_drain); 740 741 ret = -ETIMEDOUT; 742 do { 743 /* Read response queue status to ensure it is empty */ 744 uint32_t idle_status; 745 746 idle_status = mmio_read_32(SOCFPGA_F2SDRAMMGR(SIDEBANDMGR_FLAGINSTATUS0)); 747 if ((idle_status & f2s_respempty) != 0U) { 748 idle_status = mmio_read_32(SOCFPGA_F2SDRAMMGR(SIDEBANDMGR_FLAGINSTATUS0)); 749 if ((idle_status & f2s_respempty) != 0U) { 750 /* No time-out we are good! */ 751 ret = 0; 752 break; 753 } 754 } 755 756 asm("nop"); 757 758 } while (timeout-- > 0); 759 760 return ret; 761 } 762 763 int socfpga_bridges_disable(uint32_t mask) 764 { 765 int ret = 0; 766 uint32_t brg_mask = 0; 767 uint32_t noc_mask = 0; 768 uint32_t f2s_idlereq = 0; 769 uint32_t f2s_force_drain = 0; 770 uint32_t f2s_en = 0; 771 uint32_t f2s_idleack = 0; 772 uint32_t f2s_respempty = 0; 773 uint32_t f2s_cmdidle = 0; 774 775 /* Disable s2f bridge */ 776 socfpga_s2f_bridge_mask(mask, &brg_mask, &noc_mask); 777 if (brg_mask != 0U) { 778 mmio_setbits_32(SOCFPGA_SYSMGR(NOC_IDLEREQ_SET), 779 noc_mask); 780 781 mmio_write_32(SOCFPGA_SYSMGR(NOC_TIMEOUT), 1); 782 783 ret = poll_idle_status(SOCFPGA_SYSMGR(NOC_IDLEACK), 784 noc_mask, noc_mask, 300); 785 if (ret < 0) { 786 ERROR("S2F Bridge disable: Timeout idle ack\n"); 787 } 788 789 ret = poll_idle_status(SOCFPGA_SYSMGR(NOC_IDLESTATUS), 790 noc_mask, noc_mask, 300); 791 if (ret < 0) { 792 ERROR("S2F Bridge disable: Timeout idle status\n"); 793 } 794 795 mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST), brg_mask); 796 797 mmio_write_32(SOCFPGA_SYSMGR(NOC_TIMEOUT), 0); 798 } 799 800 /* Disable f2s bridge */ 801 socfpga_f2s_bridge_mask(mask, &brg_mask, &f2s_idlereq, 802 &f2s_force_drain, &f2s_en, 803 &f2s_idleack, &f2s_respempty, &f2s_cmdidle); 804 if (brg_mask != 0U) { 805 806 if (mmio_read_32(SOCFPGA_RSTMGR(BRGMODRST)) & brg_mask) { 807 /* Bridge cannot be reset twice */ 808 return 0; 809 } 810 811 /* Starts the fence and drain traffic from F2SDRAM to MPFE */ 812 mmio_setbits_32(SOCFPGA_RSTMGR(HDSKEN), 813 RSTMGR_HDSKEN_FPGAHSEN); 814 udelay(5); 815 /* Ignoring FPGA ACK as it will time-out */ 816 mmio_setbits_32(SOCFPGA_RSTMGR(HDSKREQ), 817 RSTMGR_HDSKREQ_FPGAHSREQ); 818 819 ret = poll_idle_status_by_clkcycles(SOCFPGA_RSTMGR(HDSKACK), 820 RSTMGR_HDSKACK_FPGAHSREQ, 821 RSTMGR_HDSKACK_FPGAHSREQ, 1000); 822 823 /* DISABLE F2S Bridge */ 824 mmio_setbits_32(SOCFPGA_F2SDRAMMGR(SIDEBANDMGR_FLAGOUTCLR0), 825 f2s_en); 826 udelay(5); 827 828 ret = socfpga_bridge_nongraceful_disable(mask); 829 830 /* Bridge reset */ 831 #if PLATFORM_MODEL == PLAT_SOCFPGA_STRATIX10 832 /* Software must never write a 0x1 to FPGA2SOC_MASK bit */ 833 mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST), 834 brg_mask & ~RSTMGR_FIELD(BRG, FPGA2SOC)); 835 #else 836 mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST), 837 brg_mask); 838 #endif 839 /* Re-enable traffic to SDRAM*/ 840 mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ), 841 RSTMGR_HDSKREQ_FPGAHSREQ); 842 843 mmio_setbits_32(SOCFPGA_F2SDRAMMGR(SIDEBANDMGR_FLAGOUTCLR0), 844 f2s_idlereq); 845 } 846 847 return ret; 848 } 849 850 /* CPUxRESETBASELOW */ 851 int socfpga_cpu_reset_base(unsigned int cpu_id) 852 { 853 int ret = 0; 854 uint32_t entrypoint = 0; 855 856 ret = socfpga_cpurstrelease(cpu_id); 857 858 if (ret < 0) { 859 return RSTMGR_RET_ERROR; 860 } 861 862 if (ret == RSTMGR_RET_OK) { 863 864 switch (cpu_id) { 865 case 0: 866 entrypoint = mmio_read_32(SOCFPGA_RSTMGR_CPUBASELOW_0); 867 entrypoint |= mmio_read_32(SOCFPGA_RSTMGR_CPUBASEHIGH_0) << 24; 868 break; 869 870 case 1: 871 entrypoint = mmio_read_32(SOCFPGA_RSTMGR_CPUBASELOW_1); 872 entrypoint |= mmio_read_32(SOCFPGA_RSTMGR_CPUBASEHIGH_1) << 24; 873 break; 874 875 case 2: 876 entrypoint = mmio_read_32(SOCFPGA_RSTMGR_CPUBASELOW_2); 877 entrypoint |= mmio_read_32(SOCFPGA_RSTMGR_CPUBASEHIGH_2) << 24; 878 break; 879 880 case 3: 881 entrypoint = mmio_read_32(SOCFPGA_RSTMGR_CPUBASELOW_3); 882 entrypoint |= mmio_read_32(SOCFPGA_RSTMGR_CPUBASEHIGH_3) << 24; 883 break; 884 885 default: 886 break; 887 } 888 889 mmio_write_64(PLAT_SEC_ENTRY, entrypoint); 890 } 891 892 return RSTMGR_RET_OK; 893 } 894 895 /* CPURSTRELEASE */ 896 int socfpga_cpurstrelease(unsigned int cpu_id) 897 { 898 unsigned int timeout = 0; 899 900 do { 901 /* Read response queue status to ensure it is empty */ 902 uint32_t cpurstrelease_status; 903 904 cpurstrelease_status = mmio_read_32(SOCFPGA_RSTMGR(CPURSTRELEASE)); 905 906 if ((cpurstrelease_status & RSTMGR_CPUSTRELEASE_CPUx) == cpu_id) { 907 return RSTMGR_RET_OK; 908 } 909 udelay(1000); 910 } while (timeout-- > 0); 911 912 return RSTMGR_RET_ERROR; 913 } 914