1 /* 2 * Copyright (c) 2020-2022, Intel Corporation. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <lib/mmio.h> 8 #include <platform_def.h> 9 10 #include "socfpga_emac.h" 11 #include "socfpga_plat_def.h" 12 #include "socfpga_reset_manager.h" 13 #include "socfpga_system_manager.h" 14 15 void socfpga_emac_init(void) 16 { 17 mmio_setbits_32(SOCFPGA_RSTMGR(PER0MODRST), 18 RSTMGR_PER0MODRST_EMAC0 | 19 RSTMGR_PER0MODRST_EMAC1 | 20 RSTMGR_PER0MODRST_EMAC2); 21 22 mmio_clrsetbits_32(SOCFPGA_SYSMGR(EMAC_0), 23 PHY_INTF_SEL_MSK, EMAC0_PHY_MODE); 24 mmio_clrsetbits_32(SOCFPGA_SYSMGR(EMAC_1), 25 PHY_INTF_SEL_MSK, EMAC1_PHY_MODE); 26 mmio_clrsetbits_32(SOCFPGA_SYSMGR(EMAC_2), 27 PHY_INTF_SEL_MSK, EMAC2_PHY_MODE); 28 29 mmio_clrbits_32(SOCFPGA_SYSMGR(FPGAINTF_EN_3), 30 FPGAINTF_EN_3_EMAC_MSK(0) | 31 FPGAINTF_EN_3_EMAC_MSK(1) | 32 FPGAINTF_EN_3_EMAC_MSK(2)); 33 34 mmio_clrbits_32(SOCFPGA_RSTMGR(PER0MODRST), 35 RSTMGR_PER0MODRST_EMAC0 | 36 RSTMGR_PER0MODRST_EMAC1 | 37 RSTMGR_PER0MODRST_EMAC2); 38 } 39 40