1 /* 2 * Copyright (c) 2023, MediaTek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <common/debug.h> 8 #include <drivers/spm/mt_spm_resource_req.h> 9 #include <lib/pm/mtk_pm.h> 10 #include <lpm/mt_lp_api.h> 11 #include <lpm/mt_lp_rm.h> 12 #include <mt_spm.h> 13 #include <mt_spm_cond.h> 14 #include <mt_spm_conservation.h> 15 #include <mt_spm_constraint.h> 16 #include <mt_spm_idle.h> 17 #include <mt_spm_internal.h> 18 #include <mt_spm_notifier.h> 19 #include "mt_spm_rc_api.h" 20 #include "mt_spm_rc_internal.h" 21 #include <mt_spm_reg.h> 22 #include <mt_spm_suspend.h> 23 24 #define CONSTRAINT_DRAM_ALLOW (MT_RM_CONSTRAINT_ALLOW_DRAM_S0 | \ 25 MT_RM_CONSTRAINT_ALLOW_DRAM_S1 | \ 26 MT_RM_CONSTRAINT_ALLOW_CPU_BUCK_OFF) 27 28 #define CONSTRAINT_DRAM_PCM_FLAG (SPM_FLAG_DISABLE_INFRA_PDN | \ 29 SPM_FLAG_DISABLE_VCORE_DVS | \ 30 SPM_FLAG_DISABLE_VCORE_DFS | \ 31 SPM_FLAG_SRAM_SLEEP_CTRL | \ 32 SPM_FLAG_KEEP_CSYSPWRACK_HIGH | \ 33 SPM_FLAG_DISABLE_DRAMC_MCU_SRAM_SLEEP) 34 35 #define CONSTRAINT_DRAM_PCM_FLAG1 (0) 36 37 #define CONSTRAINT_DRAM_RESOURCE_REQ (MT_SPM_SYSPLL | MT_SPM_INFRA | MT_SPM_26M) 38 39 static struct mt_spm_cond_tables cond_dram = { 40 .name = "dram", 41 .table_cg = { 42 0xFF5DD002, /* MTCMOS1 */ 43 0x0000003C, /* MTCMOS2 */ 44 0x27AF8000, /* INFRA0 */ 45 0x20010876, /* INFRA1 */ 46 0x86000640, /* INFRA2 */ 47 0x00000000, /* INFRA3 */ 48 0x80000000, /* INFRA4 */ 49 0x01002A00, /* PERI0 */ 50 0x00080000, /* VPPSYS0_0 */ 51 0x38803000, /* VPPSYS0_1 */ 52 0x00081450, /* VPPSYS1_0 */ 53 0x00003000, /* VPPSYS1_1 */ 54 0x00000000, /* VDOSYS0_0 */ 55 0x00000000, /* VDOSYS0_1 */ 56 0x000001F8, /* VDOSYS1_0 */ 57 0x000001E0, /* VDOSYS1_1 */ 58 0x00FB0007, /* VDOSYS1_2 */ 59 }, 60 .table_pll = 0U, 61 }; 62 63 static struct mt_spm_cond_tables cond_dram_res = { 64 .table_cg = { 0U }, 65 .table_pll = 0U, 66 }; 67 68 static struct constraint_status status = { 69 .id = MT_RM_CONSTRAINT_ID_DRAM, 70 .is_valid = (MT_SPM_RC_VALID_SW | 71 MT_SPM_RC_VALID_COND_CHECK | 72 MT_SPM_RC_VALID_COND_LATCH | 73 MT_SPM_RC_VALID_XSOC_BBLPM | 74 MT_SPM_RC_VALID_TRACE_TIME), 75 .is_cond_block = 0U, 76 .enter_cnt = 0U, 77 .cond_res = &cond_dram_res, 78 .residency = 0ULL, 79 }; 80 81 static unsigned short ext_status_dram; 82 83 int spm_dram_conduct(int state_id, struct spm_lp_scen *spm_lp, unsigned int *resource_req) 84 { 85 unsigned int res_req = CONSTRAINT_DRAM_RESOURCE_REQ; 86 87 if ((spm_lp == NULL) || (resource_req == NULL)) { 88 return -1; 89 } 90 91 spm_lp->pwrctrl->pcm_flags = (uint32_t)CONSTRAINT_DRAM_PCM_FLAG; 92 spm_lp->pwrctrl->pcm_flags1 = (uint32_t)CONSTRAINT_DRAM_PCM_FLAG1; 93 94 *resource_req |= res_req; 95 return 0; 96 } 97 98 bool spm_is_valid_rc_dram(unsigned int cpu, int state_id) 99 { 100 return (!(status.is_cond_block && (status.is_valid & MT_SPM_RC_VALID_COND_CHECK)) && 101 IS_MT_RM_RC_READY(status.is_valid) && 102 (IS_PLAT_SUSPEND_ID(state_id) || 103 (state_id == MT_PLAT_PWR_STATE_SYSTEM_MEM) || 104 (state_id == MT_PLAT_PWR_STATE_SYSTEM_PLL) || 105 (state_id == MT_PLAT_PWR_STATE_SYSTEM_BUS))); 106 } 107 108 static int update_rc_condition(int state_id, const void *val) 109 { 110 const struct mt_spm_cond_tables *tlb = (const struct mt_spm_cond_tables *)val; 111 const struct mt_spm_cond_tables *tlb_check = (const struct mt_spm_cond_tables *)&cond_dram; 112 113 if (tlb == NULL) { 114 return MT_RM_STATUS_BAD; 115 } 116 117 status.is_cond_block = mt_spm_cond_check(state_id, tlb, tlb_check, 118 (status.is_valid & MT_SPM_RC_VALID_COND_LATCH) ? 119 &cond_dram_res : NULL); 120 return MT_RM_STATUS_OK; 121 } 122 123 static void update_rc_clkbuf_status(const void *val) 124 { 125 unsigned int is_flight = (val) ? !!(*((unsigned int *)val) == FLIGHT_MODE_ON) : 0; 126 127 if (is_flight != 0U) { 128 spm_rc_constraint_valid_set(MT_RM_CONSTRAINT_ID_DRAM, 129 MT_RM_CONSTRAINT_ID_DRAM, 130 MT_SPM_RC_VALID_FLIGHTMODE, 131 (struct constraint_status * const)&status); 132 } else { 133 spm_rc_constraint_valid_clr(MT_RM_CONSTRAINT_ID_DRAM, 134 MT_RM_CONSTRAINT_ID_DRAM, 135 MT_SPM_RC_VALID_FLIGHTMODE, 136 (struct constraint_status * const)&status); 137 } 138 } 139 140 static void update_rc_ufs_status(const void *val) 141 { 142 unsigned int is_ufs_h8 = (val) ? !!(*((unsigned int *)val) == UFS_REF_CLK_OFF) : 0; 143 144 if (is_ufs_h8 != 0U) { 145 spm_rc_constraint_valid_set(MT_RM_CONSTRAINT_ID_DRAM, 146 MT_RM_CONSTRAINT_ID_DRAM, 147 MT_SPM_RC_VALID_UFS_H8, 148 (struct constraint_status * const)&status); 149 } else { 150 spm_rc_constraint_valid_clr(MT_RM_CONSTRAINT_ID_DRAM, 151 MT_RM_CONSTRAINT_ID_DRAM, 152 MT_SPM_RC_VALID_UFS_H8, 153 (struct constraint_status * const)&status); 154 } 155 } 156 157 static void update_rc_status(const void *val) 158 { 159 const struct rc_common_state *st; 160 161 st = (const struct rc_common_state *)val; 162 163 if (st == NULL) { 164 return; 165 } 166 167 if (st->type == CONSTRAINT_UPDATE_COND_CHECK) { 168 struct mt_spm_cond_tables * const tlb = &cond_dram; 169 170 spm_rc_condition_modifier(st->id, st->act, st->value, 171 MT_RM_CONSTRAINT_ID_DRAM, tlb); 172 } else if ((st->type == CONSTRAINT_UPDATE_VALID) || 173 (st->type == CONSTRAINT_RESIDNECY)) { 174 spm_rc_constraint_status_set(st->id, st->type, st->act, 175 MT_RM_CONSTRAINT_ID_DRAM, 176 (struct constraint_status * const)st->value, 177 (struct constraint_status * const)&status); 178 } else { 179 INFO("[%s:%d] - Unknown type: 0x%x\n", __func__, __LINE__, st->type); 180 } 181 } 182 183 int spm_update_rc_dram(int state_id, int type, const void *val) 184 { 185 int res = MT_RM_STATUS_OK; 186 187 switch (type) { 188 case PLAT_RC_UPDATE_CONDITION: 189 res = update_rc_condition(state_id, val); 190 break; 191 case PLAT_RC_CLKBUF_STATUS: 192 update_rc_clkbuf_status(val); 193 break; 194 case PLAT_RC_UFS_STATUS: 195 update_rc_ufs_status(val); 196 break; 197 case PLAT_RC_STATUS: 198 update_rc_status(val); 199 break; 200 default: 201 INFO("[%s:%d] - Do nothing for type: %d\n", __func__, __LINE__, type); 202 break; 203 } 204 205 return res; 206 } 207 208 unsigned int spm_allow_rc_dram(int state_id) 209 { 210 return CONSTRAINT_DRAM_ALLOW; 211 } 212 213 int spm_run_rc_dram(unsigned int cpu, int state_id) 214 { 215 unsigned int ext_op = MT_SPM_EX_OP_HW_S1_DETECT; 216 unsigned int allows = CONSTRAINT_DRAM_ALLOW; 217 218 ext_status_dram = status.is_valid; 219 220 if (IS_MT_SPM_RC_BBLPM_MODE(ext_status_dram)) { 221 #ifdef MT_SPM_USING_SRCLKEN_RC 222 ext_op |= MT_SPM_EX_OP_SRCLKEN_RC_BBLPM; 223 #else 224 allows |= MT_RM_CONSTRAINT_ALLOW_BBLPM; 225 #endif 226 } 227 228 #ifndef MTK_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT 229 mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_ENTER, allows | (IS_PLAT_SUSPEND_ID(state_id) ? 230 (MT_RM_CONSTRAINT_ALLOW_AP_SUSPEND) : (0U))); 231 #else 232 (void)allows; 233 #endif 234 235 if (ext_status_dram & MT_SPM_RC_VALID_TRACE_TIME) { 236 ext_op |= MT_SPM_EX_OP_TRACE_TIMESTAMP_EN; 237 } 238 239 if (IS_PLAT_SUSPEND_ID(state_id)) { 240 mt_spm_suspend_enter(state_id, 241 (MT_SPM_EX_OP_CLR_26M_RECORD | 242 MT_SPM_EX_OP_SET_WDT | 243 MT_SPM_EX_OP_SET_SUSPEND_MODE | 244 MT_SPM_EX_OP_HW_S1_DETECT), 245 CONSTRAINT_DRAM_RESOURCE_REQ); 246 } else { 247 mt_spm_idle_generic_enter(state_id, ext_op, spm_dram_conduct); 248 } 249 250 return 0; 251 } 252 253 int spm_reset_rc_dram(unsigned int cpu, int state_id) 254 { 255 unsigned int ext_op = MT_SPM_EX_OP_HW_S1_DETECT; 256 unsigned int allows = CONSTRAINT_DRAM_ALLOW; 257 258 if (IS_MT_SPM_RC_BBLPM_MODE(ext_status_dram)) { 259 #ifdef MT_SPM_USING_SRCLKEN_RC 260 ext_op |= MT_SPM_EX_OP_SRCLKEN_RC_BBLPM; 261 #else 262 allows |= MT_RM_CONSTRAINT_ALLOW_BBLPM; 263 #endif 264 } 265 266 #ifndef MTK_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT 267 mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_LEAVE, allows); 268 #else 269 (void)allows; 270 #endif 271 272 if (ext_status_dram & MT_SPM_RC_VALID_TRACE_TIME) { 273 ext_op |= MT_SPM_EX_OP_TRACE_TIMESTAMP_EN; 274 } 275 276 if (IS_PLAT_SUSPEND_ID(state_id)) { 277 mt_spm_suspend_resume(state_id, 278 (MT_SPM_EX_OP_SET_WDT | MT_SPM_EX_OP_HW_S1_DETECT), 279 NULL); 280 } else { 281 struct wake_status *waken = NULL; 282 283 if (spm_unlikely(status.is_valid & MT_SPM_RC_VALID_TRACE_EVENT)) { 284 ext_op |= MT_SPM_EX_OP_TRACE_LP; 285 } 286 mt_spm_idle_generic_resume(state_id, ext_op, &waken, NULL); 287 status.enter_cnt++; 288 289 if (spm_unlikely(status.is_valid & MT_SPM_RC_VALID_RESIDNECY)) { 290 status.residency += (waken != NULL) ? waken->tr.comm.timer_out : 0; 291 } 292 } 293 294 return 0; 295 } 296 297 int spm_get_status_rc_dram(unsigned int type, void *priv) 298 { 299 int ret = MT_RM_STATUS_OK; 300 301 if (type == PLAT_RC_STATUS) { 302 int res = 0; 303 struct rc_common_state *st = (struct rc_common_state *)priv; 304 305 if (st == NULL) { 306 return MT_RM_STATUS_BAD; 307 } 308 309 res = spm_rc_constraint_status_get(st->id, st->type, 310 st->act, MT_RM_CONSTRAINT_ID_DRAM, 311 (struct constraint_status * const)&status, 312 (struct constraint_status * const)st->value); 313 if ((res == 0) && (st->id != MT_RM_CONSTRAINT_ID_ALL)) { 314 ret = MT_RM_STATUS_STOP; 315 } 316 } 317 return ret; 318 } 319