1 /* 2 * Copyright (c) 2023, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <platform_def.h> 10 #include <sigi_def.h> 11 12 #include <common/bl_common.h> 13 #include <common/debug.h> 14 #include <common/desc_image_load.h> 15 #include <drivers/console.h> 16 #include <drivers/generic_delay_timer.h> 17 #include <drivers/ti/uart/uart_16550.h> 18 #include <lib/mmio.h> 19 #include <plat/common/platform.h> 20 #include <plat/arm/common/plat_arm.h> 21 22 static entry_point_info_t bl32_image_ep_info; 23 static entry_point_info_t bl33_image_ep_info; 24 25 /* 26 * Table of regions to map using the MMU. 27 * This doesn't include TZRAM as the 'mem_layout' argument passed to 28 * configure_mmu_elx() will give the available subset of that, 29 */ 30 const mmap_region_t plat_sigi_mmap[] = { 31 MAP_REGION_FLAT(DEVICE0_BASE, DEVICE0_SIZE, MT_DEVICE | MT_RW | MT_SECURE), 32 MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE, MT_DEVICE | MT_RW | MT_SECURE), 33 { 0 } 34 }; 35 36 const mmap_region_t *plat_sigi_get_mmap(void) 37 { 38 return plat_sigi_mmap; 39 } 40 41 unsigned int plat_get_syscnt_freq2(void) 42 { 43 return SIGI_OSC24M_CLK_IN_HZ; 44 } 45 46 /******************************************************************************* 47 * Return a pointer to the 'entry_point_info' structure of the next image for 48 * the security state specified. BL33 corresponds to the non-secure image type 49 * while BL32 corresponds to the secure image type. A NULL pointer is returned 50 * if the image does not exist. 51 ******************************************************************************/ 52 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 53 { 54 entry_point_info_t *next_image_info; 55 56 //assert(sec_state_is_valid(type)); 57 next_image_info = (type == NON_SECURE) ? \ 58 &bl33_image_ep_info : &bl32_image_ep_info; 59 60 /* None of the images on this platform can have 0x0 as the entrypoint */ 61 if (next_image_info->pc) 62 return next_image_info; 63 else 64 return NULL; 65 } 66 67 /* 68 * Set the build time defaults,if we can't find any config data. 69 */ 70 static inline void bl31_set_default_config(void) 71 { 72 bl32_image_ep_info.pc = (uintptr_t)BL32_BASE; 73 bl32_image_ep_info.spsr = (uint32_t)arm_get_spsr_for_bl32_entry(); 74 bl33_image_ep_info.pc = (uintptr_t)plat_get_ns_image_entrypoint(); 75 bl33_image_ep_info.spsr = (uint32_t)SPSR_64(MODE_EL2, MODE_SP_ELX, 76 DISABLE_ALL_EXCEPTIONS); 77 } 78 79 static void sigi_print_platform_name(void) 80 { 81 NOTICE("ATF running on %s\n", PLATFORM_NAME); 82 } 83 84 void sigi_config_setup(void) 85 { 86 sigi_print_platform_name(); 87 88 generic_delay_timer_init(); 89 } 90 91 /******************************************************************************* 92 * Perform any BL3-1 early platform setup. Here is an opportunity to copy 93 * parameters passed by the calling EL (S-EL1 in BL2 & EL3 in BL1) before they 94 * are lost (potentially). This needs to be done before the MMU is initialized 95 * so that the memory layout can be used while creating page tables. 96 * BL2 has flushed this information to memory, so we are guaranteed to pick up 97 * good data. 98 ******************************************************************************/ 99 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 100 u_register_t arg2, u_register_t arg3) 101 { 102 sigi_console_init(); 103 104 /* Initialize the platform config for future decision making */ 105 sigi_config_setup(); 106 /* There are no parameters from BL2 if BL31 is a reset vector */ 107 assert(arg0 == 0U); 108 assert(arg1 == 0U); 109 110 /* 111 * Do initial security configuration to allow DRAM/device access. On 112 * Base Sigi only DRAM security is programmable (via TrustZone), but 113 * other platforms might have more programmable security devices 114 * present. 115 */ 116 117 /* Populate common information for BL32 and BL33 */ 118 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); 119 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 120 SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0); 121 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 122 123 bl31_set_default_config(); 124 125 VERBOSE("BL31: early platform setup\n"); 126 NOTICE("BL31: Secure code at 0x%08lx\n", bl32_image_ep_info.pc); 127 NOTICE("BL31: Non secure code at 0x%08lx\n", bl33_image_ep_info.pc); 128 } 129 130 /******************************************************************************* 131 * Perform any BL3-1 platform setup code 132 ******************************************************************************/ 133 void bl31_platform_setup(void) 134 { 135 /* Initialize the gic cpu and distributor interfaces */ 136 plat_sigi_gic_init(); 137 } 138 139 /******************************************************************************* 140 * Perform the very early platform specific architectural setup here. At the 141 * moment this is only intializes the mmu in a quick and dirty way. 142 ******************************************************************************/ 143 void bl31_plat_arch_setup(void) 144 { 145 const mmap_region_t bl_regions[] = { 146 MAP_REGION_FLAT(BL31_BASE, BL31_END - BL31_BASE, 147 MT_MEMORY | MT_RW | MT_SECURE), 148 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, 149 MT_CODE | MT_SECURE), 150 MAP_REGION_FLAT(BL_RO_DATA_BASE, BL_RO_DATA_END - BL_RO_DATA_BASE, MT_RO_DATA| MT_SECURE), 151 MAP_REGION_FLAT(SHARED_RAM_BASE, SHARED_RAM_SIZE, MT_MEMORY | MT_RW | MT_SECURE), 152 {0} 153 }; 154 setup_page_tables(bl_regions, plat_sigi_get_mmap()); 155 enable_mmu_el3(0); 156 } 157