1 /* 2 * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <inttypes.h> 9 #include <stdint.h> 10 11 #include <libfdt.h> 12 13 #include <platform_def.h> 14 #include <arch_helpers.h> 15 #include <common/bl_common.h> 16 #include <lib/mmio.h> 17 #include <lib/xlat_tables/xlat_mmu_helpers.h> 18 #include <lib/xlat_tables/xlat_tables_defs.h> 19 #include <lib/xlat_tables/xlat_tables_v2.h> 20 #include <plat/common/platform.h> 21 #include <common/fdt_fixup.h> 22 #include <common/fdt_wrappers.h> 23 #include <libfdt.h> 24 25 #include <drivers/arm/gicv2.h> 26 27 #include <rpi_shared.h> 28 29 /* 30 * Fields at the beginning of armstub8.bin. 31 * While building the BL31 image, we put the stub magic into the binary. 32 * The GPU firmware detects this at boot time, clears that field as a 33 * confirmation and puts the kernel and DT address in the following words. 34 */ 35 extern uint32_t stub_magic; 36 extern uint32_t dtb_ptr32; 37 extern uint32_t kernel_entry32; 38 39 static const gicv2_driver_data_t rpi4_gic_data = { 40 .gicd_base = RPI4_GIC_GICD_BASE, 41 .gicc_base = RPI4_GIC_GICC_BASE, 42 }; 43 44 /* 45 * To be filled by the code below. At the moment BL32 is not supported. 46 * In the future these might be passed down from BL2. 47 */ 48 static entry_point_info_t bl32_image_ep_info; 49 static entry_point_info_t bl33_image_ep_info; 50 51 /******************************************************************************* 52 * Return a pointer to the 'entry_point_info' structure of the next image for 53 * the security state specified. BL33 corresponds to the non-secure image type 54 * while BL32 corresponds to the secure image type. A NULL pointer is returned 55 * if the image does not exist. 56 ******************************************************************************/ 57 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 58 { 59 entry_point_info_t *next_image_info; 60 61 assert(sec_state_is_valid(type) != 0); 62 63 next_image_info = (type == NON_SECURE) 64 ? &bl33_image_ep_info : &bl32_image_ep_info; 65 66 /* None of the images can have 0x0 as the entrypoint. */ 67 if (next_image_info->pc) { 68 return next_image_info; 69 } else { 70 return NULL; 71 } 72 } 73 74 uintptr_t plat_get_ns_image_entrypoint(void) 75 { 76 #ifdef PRELOADED_BL33_BASE 77 return PRELOADED_BL33_BASE; 78 #else 79 /* Cleared by the GPU if kernel address is valid. */ 80 if (stub_magic == 0) 81 return kernel_entry32; 82 83 WARN("Stub magic failure, using default kernel address 0x80000\n"); 84 return 0x80000; 85 #endif 86 } 87 88 static uintptr_t rpi4_get_dtb_address(void) 89 { 90 #ifdef RPI3_PRELOADED_DTB_BASE 91 return RPI3_PRELOADED_DTB_BASE; 92 #else 93 /* Cleared by the GPU if DTB address is valid. */ 94 if (stub_magic == 0) 95 return dtb_ptr32; 96 97 WARN("Stub magic failure, DTB address unknown\n"); 98 return 0; 99 #endif 100 } 101 102 static void ldelay(register_t delay) 103 { 104 __asm__ volatile ( 105 "1:\tcbz %0, 2f\n\t" 106 "sub %0, %0, #1\n\t" 107 "b 1b\n" 108 "2:" 109 : "=&r" (delay) : "0" (delay) 110 ); 111 } 112 113 /******************************************************************************* 114 * Perform any BL31 early platform setup. Here is an opportunity to copy 115 * parameters passed by the calling EL (S-EL1 in BL2 & EL3 in BL1) before 116 * they are lost (potentially). This needs to be done before the MMU is 117 * initialized so that the memory layout can be used while creating page 118 * tables. BL2 has flushed this information to memory, so we are guaranteed 119 * to pick up good data. 120 ******************************************************************************/ 121 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 122 u_register_t arg2, u_register_t arg3) 123 124 { 125 /* 126 * LOCAL_CONTROL: 127 * Bit 9 clear: Increment by 1 (vs. 2). 128 * Bit 8 clear: Timer source is 19.2MHz crystal (vs. APB). 129 */ 130 mmio_write_32(RPI4_LOCAL_CONTROL_BASE_ADDRESS, 0); 131 132 /* LOCAL_PRESCALER; divide-by (0x80000000 / register_val) == 1 */ 133 mmio_write_32(RPI4_LOCAL_CONTROL_PRESCALER, 0x80000000); 134 135 /* Early GPU firmware revisions need a little break here. */ 136 ldelay(100000); 137 138 /* Initialize the console to provide early debug support. */ 139 rpi3_console_init(); 140 141 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); 142 bl33_image_ep_info.spsr = rpi3_get_spsr_for_bl33_entry(); 143 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 144 145 #if RPI3_DIRECT_LINUX_BOOT 146 # if RPI3_BL33_IN_AARCH32 147 /* 148 * According to the file ``Documentation/arm/Booting`` of the Linux 149 * kernel tree, Linux expects: 150 * r0 = 0 151 * r1 = machine type number, optional in DT-only platforms (~0 if so) 152 * r2 = Physical address of the device tree blob 153 */ 154 VERBOSE("rpi4: Preparing to boot 32-bit Linux kernel\n"); 155 bl33_image_ep_info.args.arg0 = 0U; 156 bl33_image_ep_info.args.arg1 = ~0U; 157 bl33_image_ep_info.args.arg2 = rpi4_get_dtb_address(); 158 # else 159 /* 160 * According to the file ``Documentation/arm64/booting.txt`` of the 161 * Linux kernel tree, Linux expects the physical address of the device 162 * tree blob (DTB) in x0, while x1-x3 are reserved for future use and 163 * must be 0. 164 */ 165 VERBOSE("rpi4: Preparing to boot 64-bit Linux kernel\n"); 166 bl33_image_ep_info.args.arg0 = rpi4_get_dtb_address(); 167 bl33_image_ep_info.args.arg1 = 0ULL; 168 bl33_image_ep_info.args.arg2 = 0ULL; 169 bl33_image_ep_info.args.arg3 = 0ULL; 170 # endif /* RPI3_BL33_IN_AARCH32 */ 171 #endif /* RPI3_DIRECT_LINUX_BOOT */ 172 } 173 174 void bl31_plat_arch_setup(void) 175 { 176 /* 177 * Is the dtb_ptr32 pointer valid? If yes, map the DTB region. 178 * We map the 2MB region the DTB start address lives in, plus 179 * the next 2MB, to have enough room for expansion. 180 */ 181 if (stub_magic == 0) { 182 unsigned long long dtb_region = dtb_ptr32; 183 184 dtb_region &= ~0x1fffff; /* Align to 2 MB. */ 185 mmap_add_region(dtb_region, dtb_region, 4U << 20, 186 MT_MEMORY | MT_RW | MT_NS); 187 } 188 /* 189 * Add the first page of memory, which holds the stub magic, 190 * the kernel and the DT address. 191 * This also holds the secondary CPU's entrypoints and mailboxes. 192 */ 193 mmap_add_region(0, 0, 4096, MT_NON_CACHEABLE | MT_RW | MT_SECURE); 194 195 rpi3_setup_page_tables(BL31_BASE, BL31_END - BL31_BASE, 196 BL_CODE_BASE, BL_CODE_END, 197 BL_RO_DATA_BASE, BL_RO_DATA_END 198 #if USE_COHERENT_MEM 199 , BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END 200 #endif 201 ); 202 203 enable_mmu_el3(0); 204 } 205 206 /* 207 * Remove the FDT /memreserve/ entry that covers the region at the very 208 * beginning of memory (if that exists). This is where the secondaries 209 * originally spin, but we pull them out there. 210 * Having overlapping /reserved-memory and /memreserve/ regions confuses 211 * the Linux kernel, so we need to get rid of this one. 212 */ 213 static void remove_spintable_memreserve(void *dtb) 214 { 215 uint64_t addr, size; 216 int regions = fdt_num_mem_rsv(dtb); 217 int i; 218 219 for (i = 0; i < regions; i++) { 220 if (fdt_get_mem_rsv(dtb, i, &addr, &size) != 0) { 221 return; 222 } 223 if (size == 0U) { 224 return; 225 } 226 /* We only look for the region at the beginning of DRAM. */ 227 if (addr != 0U) { 228 continue; 229 } 230 /* 231 * Currently the region in the existing DTs is exactly 4K 232 * in size. Should this value ever change, there is probably 233 * a reason for that, so inform the user about this. 234 */ 235 if (size == 4096U) { 236 fdt_del_mem_rsv(dtb, i); 237 return; 238 } 239 WARN("Keeping unknown /memreserve/ region at 0, size: %" PRId64 "\n", 240 size); 241 } 242 } 243 244 static void rpi4_prepare_dtb(void) 245 { 246 void *dtb = (void *)rpi4_get_dtb_address(); 247 uint32_t gic_int_prop[3]; 248 int ret, offs; 249 250 /* Return if no device tree is detected */ 251 if (fdt_check_header(dtb) != 0) 252 return; 253 254 ret = fdt_open_into(dtb, dtb, 0x100000); 255 if (ret < 0) { 256 ERROR("Invalid Device Tree at %p: error %d\n", dtb, ret); 257 return; 258 } 259 260 if (dt_add_psci_node(dtb)) { 261 ERROR("Failed to add PSCI Device Tree node\n"); 262 return; 263 } 264 265 if (dt_add_psci_cpu_enable_methods(dtb)) { 266 ERROR("Failed to add PSCI cpu enable methods in Device Tree\n"); 267 return; 268 } 269 270 /* 271 * Remove the original reserved region (used for the spintable), and 272 * replace it with a region describing the whole of Trusted Firmware. 273 */ 274 remove_spintable_memreserve(dtb); 275 if (fdt_add_reserved_memory(dtb, "atf@0", 0, 0x80000)) 276 WARN("Failed to add reserved memory nodes to DT.\n"); 277 278 offs = fdt_node_offset_by_compatible(dtb, 0, "arm,gic-400"); 279 gic_int_prop[0] = cpu_to_fdt32(1); // PPI 280 gic_int_prop[1] = cpu_to_fdt32(9); // PPI #9 281 gic_int_prop[2] = cpu_to_fdt32(0x0f04); // all cores, level high 282 fdt_setprop(dtb, offs, "interrupts", gic_int_prop, 12); 283 284 offs = fdt_path_offset(dtb, "/chosen"); 285 fdt_setprop_string(dtb, offs, "stdout-path", "serial0"); 286 287 ret = fdt_pack(dtb); 288 if (ret < 0) 289 ERROR("Failed to pack Device Tree at %p: error %d\n", dtb, ret); 290 291 clean_dcache_range((uintptr_t)dtb, fdt_blob_size(dtb)); 292 INFO("Changed device tree to advertise PSCI.\n"); 293 } 294 295 void bl31_platform_setup(void) 296 { 297 rpi4_prepare_dtb(); 298 299 /* Configure the interrupt controller */ 300 gicv2_driver_init(&rpi4_gic_data); 301 gicv2_distif_init(); 302 gicv2_pcpu_distif_init(); 303 gicv2_cpuif_enable(); 304 } 305